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https://designers-guide.org/forum/YaBB.pl Design Languages >> Verilog-AMS >> which one is mostly preferable in between ?: and if else in verilog design https://designers-guide.org/forum/YaBB.pl?num=1382419756 Message started by Kotesh on Oct 21st, 2013, 10:29pm |
Title: which one is mostly preferable in between ?: and if else in verilog design Post by Kotesh on Oct 21st, 2013, 10:29pm In verilog design, we have ?: operator and if..else statement. for ex: c = foo ? a:b for ex: if (foo) c = a; else c = b; which one of the above code is preferable in verilog design prospective - - - Updated - - - and what is the difference between them. Shall i use ?: operator in design rather than if..else . If Yes, why? |
Title: Re: which one is mostly preferable in between ?: and if else in verilog design Post by Geoffrey_Coram on Nov 5th, 2013, 8:16am I don't think it matters. Is there any difference when doing the corresponding operations in C? |
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