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https://designers-guide.org/forum/YaBB.pl Design Languages >> Verilog-AMS >> a simple inverter verilogA module in Hspice simulation https://designers-guide.org/forum/YaBB.pl?num=1382927056 Message started by xiaota on Oct 27th, 2013, 7:24pm |
Title: a simple inverter verilogA module in Hspice simulation Post by xiaota on Oct 27th, 2013, 7:24pm module V_not(in,out); input in; output out; electrical in,out; parameter real vout_high = 5, vout_low = 0 from (-inf:vout_high), vth = 1.4, tdelay = 5n from [0:inf), trise = 1n from [0:inf), tfall = 1n from [0:inf); analog begin @(cross(V(in) - vth, +1)); V(out) <+ transition(vout_high,tdelay,trise,tfall); @(cross(V(in) - vth, -1)); V(out) <+ transition(vout_low,tdelay,trise,tfall); end endmodule any question with the above inv module when I use it in Hspice ,I can not get the right result .hdl '.\not.va' Xinv A Y V_not *Vin A 0 pat(5 0 0 100n 100n 100m b1010 rb=0 r=-1) Vin A 0 pwl(0 0 250m 5 500m 0) .tran 1m 500m .end |
Title: Re: a simple inverter verilogA module in Hspice simulation Post by Geoffrey_Coram on Nov 5th, 2013, 8:25am The simulator should not allow you to put a contribution V(out) <+ inside a cross event. And actually, now that I look at your code, you aren't; what you really have is Code:
So, the cross events only control the timesteps, and the contributions are always made, and I expect you end up with V(out) <+ vout_high + vout_low; You need a variable: Code:
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