The Designer's Guide Community Forum

The Designer's Guide Community Forum
https://designers-guide.org/forum/YaBB.pl
Design Languages >> Verilog-AMS >> PLL Modeling at 10GHz
https://designers-guide.org/forum/YaBB.pl?num=1383037013

Message started by pcardoso73 on Oct 29^th, 2013, 1:56am

Title: PLL Modeling at 10GHz
Post by pcardoso73 on Oct 29^th, 2013, 1:56am

Dear all,

I am starting to design a BIST block for a PLL. I would like to receive the output signal of the PLL, so I could dimension the BIST circuitry.

To achieve this, I thought of doing a model of the PLL using Verilog A/AMS. The model should include phase noise, and be capable of delivering a 10 GHz signal with a phase noise of -140dBc/Hz @ 20 MHz.

After reading one of Ken's white paper, that is the base for the 160 MHz PLL, I was wondering if I could use a similar code to generate a 10 GHz PLL.

Some questions:
1 - The value of the "seed" for the Jitter calculation is different all the time. Is this a random number? If it isn't how is it calculated ?

2 - The mentioned PLL (160 MHz eg. at Cadence) uses a ring oscillator based VCO. How can I use an LC tank oscillator instead that outputs 4 phases ?

Thanks to all.

Best regards,
Pedro