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Design >> Mixed-Signal Design >> Sample and Hold
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Message started by aaron_do on Nov 1^st, 2013, 1:23am

Title: Sample and Hold
Post by aaron_do on Nov 1^st, 2013, 1:23am

Hi all,

suppose I have an 8-bit flash ADC which consists of a SHA followed by a bank of comparators. Assume that the comparators are free running and not clocked. My question is, what is stopping me from removing the SHA and sampling the output after the comparators? What are the implications in terms of noise etc? Any issues with the comparator which make this impractical?

thanks,
Aaron

Title: Re: Sample and Hold
Post by sheldon on Nov 8^th, 2013, 6:13am

Aaron,

You don't mention how fast you want to run the ADC. Given that it is
a flash, the implication is that it needs to run fast. One issue is that
comparator gain is proportional to overdrive. As a result, the
comparator that needs to make the key decision is also the slowest
comparator and you can't sample until the comparator decides.
Another issues is that the input signal is not stable, that is, without
a S/H the input can slew while the comparators are trying to decide.
Due to delay, process variation, etc. more than one comparator
can be saying "I'm the one". The bottom line is that a flash ADC
without an S/H is almost always slower than a flash ADC with a S/H.

We haven't even gotten to the issue practical issue of layout,
most designs are folded to improve the form factor. Folding
the ADC into four banks of 6 bit ADCs will cause clock skews
that will post comparator sampling unfeasible.

Sheldon

Title: Re: Sample and Hold
Post by loose-electron on Dec 31^st, 2013, 11:06am

you have lost your phase integrity of your amplitude sample.

Comparators at different input bias points responds with different amounts of time.

net result will not be seen at slow speeds then as you run faster it will show up in INL-DNL characteristics and get progressively worse as that response time variance becomes more significant

Title: Re: Sample and Hold
Post by yuvan on Jan 2^nd, 2014, 4:30am

Generally we do S/H followed by quantization since S/H is highly non-linear process. So, if Quantization is done first then output which is highly non-linear & on top of it, if you are doing S/H on top of it, then you will have your signal frequency spread throughtout ur fft plot. Although theoritically possible, it's not done generally in practical scenerios.