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Design >> Analog Design >> How to sizing the transistor in the analog circuit
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Message started by watt.xu on Nov 3^rd, 2013, 6:56am

Title: How to sizing the transistor in the analog circuit
Post by watt.xu on Nov 3^rd, 2013, 6:56am

Hi Guys:
I am a freshman in IC design. I confronted the sizing problem in biasing, start-up, CMFB, amflifier circuit.
Is there any rule of thumb, to sizing the W/L in every section.
For example, I know for current mirror we commonly use larger vdsat (smaller gm/id), for cascode small vdsat (larger gm/id). However, in light of gm, vdsat we expected, We calculate the W/L. The transisor is commonly not all in saturation. How could we deal with this situation. Is there any rules for tuning the W/L, and getting the gm and vdsat I needed.

Thanks guys :D

Watt

Title: Re: How to sizing the transistor in the analog circuit
Post by analog geek on Nov 3^rd, 2013, 10:18am

Hi..
well i didnt understand what you want to do first...aspect ratio is inversely related to overdrive voltage of transistor..u can get their relationship from current equation also....it depends on what u want your transistor to do and to work in particular region....if u want more current u can increase aspect ration but that will affect ur vds sat. so u can either first fix ur current then get vds sat and u can find aspect ration..
there r many ways to do that..also if u know gm and id u can get minimum aspect ratio.
hope that helps

Title: Re: How to sizing the transistor in the analog circuit
Post by watt.xu on Nov 3^rd, 2013, 8:58pm

Guy, Thank you.
I am sorry for my twisted description. To design an amplifier, I got the input transistor gm from the specs. I just wanna know whether there are some rule of the thumb on how to decide the every transistor's vdsat, furthermore the size of the transistors, especially the length.~~ btw, How to tune the W/L ratio? is there any good advices?

thank you

Title: Re: How to sizing the transistor in the analog circuit
Post by harpoon on Nov 4^th, 2013, 12:18am

hi watt

a very general rule of thumb is to size all transistors to have a gm/i of ~10.

then for more speed, you size it greater than 10, and use minimum L

for mirrors, use large-ish L, in the order of 1u (on a 0.13um/0.18um process) to get good matching.

for low flicker noise, use large WxL area.

One thing to start thinking is about layout. It looks neater when transistors have uniform dimensions (e.g. use L=1u, 2u, etc ... rather than 1.12u, 2.38u etc ...)

the most crucial part of the design (and most often forgotten) is not the sizing of the devices, but rather the BIASING.

One good book to follow is ...
CMOS: Circuit Design, Layout, and Simulation
R. Jacob Baker

i think he also has some lectures which you can follow online ...

good luck !

Title: Re: How to sizing the transistor in the analog circuit
Post by jockeymonto on Nov 4^th, 2013, 12:47am

Hi watt,

You are asking a very naive question. W/L is all that designers want to hide, otherwise amplifier configurations can be found every where. It depends which IC technology you are using. If you are working with old technologies like 0.5um or so a text book approach could be handy. (See Razavi's Design of analog CMOS Integrated Circuits...may be page 300). If you are working in submicron technologies gm/Id approach is suitable. Consult the notes of Professor Bernard Boser. Google his notes and use the amplifier design methodology he discussed. There is no general rule of thum, intuition and experience come in handy!

Title: Re: How to sizing the transistor in the analog circuit
Post by watt.xu on Nov 4^th, 2013, 4:18pm

Thank you harpoon and jockeymoon, your advices are terrific great. Thanks a lot.

gm/id is also a good way to design, I am a new learner. Maybe I need to train my intuition.

Title: Re: How to sizing the transistor in the analog circuit
Post by harpoon on Nov 4^th, 2013, 11:49pm

no prob watt ... i was once in your shoes ...

just remember 3 rules ...

BIASING BIASING BIASING !

Title: Re: How to sizing the transistor in the analog circuit
Post by analog_rf on Nov 26^th, 2013, 5:39am

What i would advice is to initially get a feel of how the transistor vgs as well as vds behave in simple circuits. Firstly get hold of bias blocks and try putting the transistors in sat by modifying the gate bias, have a feel for how you sum up all the voltages from supply and reach ground.Razavi as well as baker are very good texts with baker being more design oriented.