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Design >> Analog Design >> Low drop out voltage regulator
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Message started by analog geek on Nov 16^th, 2013, 4:53pm

Title: Low drop out voltage regulator
Post by analog geek on Nov 16^th, 2013, 4:53pm

I am working on 90 nm LDOs. I am working on to convert 1.8 v to 0.8 volt range..any suggestions will be helpful.
Thanks

Title: Re: Low drop out voltage regulator
Post by analog_rf on Nov 26^th, 2013, 6:34am

please let us know what you need specifically. Eg:what specifications you need to achieve ,what application is it going to be used(eg:pll vco etc). Noise requirements,PSRR.

Title: Re: Low drop out voltage regulator
Post by venkatesh juturu on Nov 27^th, 2013, 9:10pm

hi sir,
i am designing VCO in cadence-virtuoso-ADE using gpdk180nm
for the ckt shown as i got op waveform as shown and i changed corresponding w/l ratio and vdd i got another waveform
my question how to stabilize the output waveform
help in this regard
thank in advance

Title: Re: Low drop out voltage regulator
Post by venkatesh juturu on Nov 27^th, 2013, 9:11pm

the output waveform

Title: Re: Low drop out voltage regulator
Post by venkatesh juturu on Nov 27^th, 2013, 9:13pm

the modified w/l output

Title: Re: Low drop out voltage regulator
Post by dave_dave on Nov 27^th, 2013, 11:40pm

hi venkatesh,

what happens if you increase your simulation time? It looks like your system is not settling within your chosen simulation time.
You should also have a look at the amplitude of your signal: it's in the picovolt range, so it is not really a signal at all.

p.s. the topic does not really fit to LDOs ;)

greets
dave

Title: Re: Low drop out voltage regulator
Post by analog_rf on Nov 29^th, 2013, 8:12pm

looks like with increased w/l your circuit is indeed oscillating.Please increase the simulation time and allow the output to settle to its final value which will be limited by the non-linearities of the circuit.what vco topology are you trying to design and what are your design requirements?eg:output freq,output phase noise@1Mhz etc.