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Design >> Analog Design >> Possible solutions to Input parasitic capacitance problem
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Message started by indra0804 on Nov 19^th, 2013, 12:44am

Title: Possible solutions to Input parasitic capacitance problem
Post by indra0804 on Nov 19^th, 2013, 12:44am

Hi experts,

I am designing a SAR ADC in gpdk 180 nm technology. Now, I have designed all the sub-blocks of a SAR ADC like comparator, SAR logic etc. Now, the problem that I am facing is that the DACout voltage is not settling to exact voltage values that they are supposed to during the clock on state. In the clock off state, the DACOut voltages settle to prpper values.

Now, after analysis, I have found that the parasitic capacitance of the comparator is causing the issue. As the unit capacitance of the DAC is comparable to the parasitic cap of my designed comparator, charge sharing is happening. The reason I am so sure is that if I increase the unit capacitance of my DAC 10 times, voltages settle perfectly. But, I can't increase the unit capacitance value at this point because of the area and power specifications that I need to meet. Another way around the problem can be to redesign the comparator to ensure less parasitic cap at the input side. This can be one option but I am not sure about the extent of parasitic cap reduction that would be possible.

My question is, is there any other solution to this problem apart from redesigning either the comparator or the DAC?? Like, is there any way by which I can separate the two blocks in a way so that the DAC does not face the parasitic capacitance of the comparator side by using some sort of buffer or voltage follower may be.....please suggest everyone. I am using DAC unit capacitance as 10fF.

Thanks & Regards,

Indrajit