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The Designer's Guide Community Forum
https://designers-guide.org/forum/YaBB.pl Design >> Analog Design >> phase plot of an amplifier https://designers-guide.org/forum/YaBB.pl?num=1384858995 Message started by GaAs_si on Nov 19th, 2013, 3:03am |
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Title: phase plot of an amplifier Post by GaAs_si on Nov 19th, 2013, 3:03am Hi all, I designed an op amp phase is not starting at 0° or 180° can someone please explain why it’s happening like this ? Thank you. |
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Title: Re: phase plot of an amplifier Post by tm123 on Nov 19th, 2013, 1:30pm It appears you have 2 AC sources on at the same time. Try turning off the AC signal on source V28. |
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Title: Re: phase plot of an amplifier Post by aaron_do on Nov 19th, 2013, 5:07pm I think its because of your extremely large L and C. It should be nothing to worry about. You could try plotting your frequency response down to a much lower frequency (microHertz for example). Aaron |
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Title: Re: phase plot of an amplifier Post by Tiger_ITRI on Nov 20th, 2013, 5:00am By seeing your gain-plot and phase-plot, I think you are desinging a high gain amplifier. A high gain amplifier, more than 100dB, the first pole may at "negative-frequency" when you apply compensation capacitor. So, if the first pole at negative-freuency your phase-plot is not start from 0deg or 180deg. But this is not the only reason that your phase-plot isn't start from 0deg or 180deg. You can check the gain-plot and pahse-plot near dc frequency, there maybe a RHP-zero at dc frequecy. You should still check that too. Hope you are doing well. :-? |
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Title: Re: phase plot of an amplifier Post by GaAs_si on Nov 20th, 2013, 5:33am Thank you Tim .I turned off the AC signal on source V28. Still phase plot is not starting at 0° or 180°. New Graphs are attached below file. Thank You |
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Title: Re: phase plot of an amplifier Post by GaAs_si on Nov 20th, 2013, 5:51am Thank you Aaron & Tiger_ITRI. I plotted frequency response down to a much lower frequency . Graphs are attached but I’m unable to understand that response . Thank you |
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Title: Re: phase plot of an amplifier Post by tm123 on Nov 20th, 2013, 6:39am OK it looks like that V28 AC source was effecting your result but removing it did not answer your question. The frequency response has a zero at low frequency most likely caused by the LC you use to break the loop. Are you able to run STB analysis? If so I would highly advise using a stability probe called IPROBE from analogLib and running the STB analysis to find the gain/phase margin. |
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Title: Re: phase plot of an amplifier Post by Tiger_ITRI on Nov 21st, 2013, 2:01am Yes, you can trying STB analysis and compared these two simulation result. By the way, if a amplifier is designed rail-to-rail input stage, there maybe zeros at frequency spectrum. |
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Title: Re: phase plot of an amplifier Post by GaAs_si on Nov 21st, 2013, 4:56am Hi Tim & Tiger_ITRI Thank you. I ran STB analysis using IPROBE from analogLib frequency “1 to 1T Hz” and “1n to 1T Hz” I am attaching Those graphs & set up. It’s not designed for rail-to-rail input stage. Thank you |
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Title: Re: phase plot of an amplifier Post by Ken Kundert on Nov 21st, 2013, 2:14pm Never, ever, try to simulate loop gain by breaking the loop. It always gives the wrong answer. There are many creative ways to break the loop: using extremely large capacitors and inductors in the feedback loop is one of those ways. People try to tell themselves it is okay because it only breaks the loop only during AC analysis, but the result is the same: no conclusions can be drawn about the stability of the circuit because you changed the circuit. The results of this simulation is meaningless. If you are using Spectre, learn to use the stb analysis. If using some other simulator, read http://www.kenkundert.com/docs/cd2001-01.pdf and implement it in your simulator. -Ken |
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Title: Re: phase plot of an amplifier Post by aaron_do on Nov 21st, 2013, 5:27pm Hi Tiger_ITRI, Quote:
What exactly do you mean here? At zero frequency the concept of phase doesn't have any meaning as far as I understand it. Sorry if I misunderstood your point... Aaron |
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Title: Re: phase plot of an amplifier Post by Tiger_ITRI on Nov 21st, 2013, 6:59pm Hi, aaron_do: The meaning of that I mentioned before is if an amplifier is high gain, such as more than 100dB, these amplifiers may be desinged by applying cascaed techniques, such as chopper or chopper-stabilized, these techniques usually need higher level and robust compensation techniques such as nested-miller frequency compensation ,NMC ,MNMC...etc. By using that techniques, the dominant-pole is much lower than a gerneral operational amplifier, usually, affter compensation, the dominat-pole may not appear in positive spectrum, because it move to negative-frequency axis by milller pole-splitting theorem. Have a nice day~ |
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Title: Re: phase plot of an amplifier Post by aaron_do on Nov 21st, 2013, 9:42pm Hi Tiger_ITRI, when you lower the dominant pole frequency, it won't become negative. It may move to 0.0001 Hz for example, but not -10 Hz. As I understand it, the bode plot itself is symmetric around 0 Hz for real signals (I believe its rotational symmetry for phase). Another thing is 0 Hz implies DC or never changing (ever). In this case, phase has no meaning. Feel free to correct me if you think I'm wrong. regards, Aaron |
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Title: Re: phase plot of an amplifier Post by Tiger_ITRI on Nov 22nd, 2013, 1:12am Hi, aaron_do: I think I can agree with you. So, I should correct that I mentioned before. Please any one who visist this board, don't follow the concept that I posted before. Many thanks. |
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Title: Re: phase plot of an amplifier Post by nrk1 on Nov 23rd, 2013, 8:43pm Though I am not as pessimistic as Ken about breaking the loop, the way it is done here is the trouble. At 1Hz, 1MH inductor has an impedance of "only" 2pi MOhms. Your gain at low frequencies is about gm*sL, which is why you have an extra phase lead of 90 degrees and a magnitude rising at 20dB per decade. 1GH or 1TH inductor should fix this. It is not only the cutoff frequency of the breaking network that matters, but also the impedance it presents to the circuit. |
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Title: Re: phase plot of an amplifier Post by Ken Kundert on Nov 24th, 2013, 12:18am nrk1, You've got it wrong. The issue is not the inductor is not large enough to break the loop. The issue is that it modifies the loop. As such, the loop gain you measure is not the actual loop gain of your circuit. The difference between the measured and actual loop gain is small at log frequencies, and so generally looks reasonable, but is often quite substantial at high frequencies. The error is quite substantial at the frequencies where you would measure phase and gain margin. -Ken |
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Title: Re: phase plot of an amplifier Post by Frank Wiedmann on Nov 25th, 2013, 12:52am aaron_do wrote on Nov 21st, 2013, 9:42pm:
At 0 Hz, the phase can be either 0 degrees (for a positive value) or 180 degrees (for a negative value). |
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Title: Re: phase plot of an amplifier Post by Frank Wiedmann on Nov 25th, 2013, 12:55am Ken Kundert wrote on Nov 21st, 2013, 2:14pm:
You can also take a look at my implementation at https://sites.google.com/site/frankwiedmann/loopgain. |
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Title: Re: phase plot of an amplifier Post by aaron_do on Nov 25th, 2013, 4:20am Quote:
At 0 Hz, the phase can be either 0 degrees (for a positive value) or 180 degrees (for a negative value). [/quote] saying a signal that never changes in time has a phase is debatable...anyway you've been doing this longer than me and you have a nice website...so I'll just concede the point :P |
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Title: Re: phase plot of an amplifier Post by nrk1 on Nov 25th, 2013, 4:58am Yes, I agree that breaking the loop modifies the circuit. In this case, if Cin of the opamp is comparable to the load(5pF), it'll surely modify it. Also, in this particular case, the unity gain frequency is about 10MHz. In any case, the original question was about the low frequency behavior of loop gain(the phase not being 180 degrees from the inverting input to the ouptut). With the LC circuit used to break the loop, about the only impedance seen at low frequencies (~ 1Hz) is the inductor. the 100F capacitor is practically a short, other capacitors are open circuits, and the internal output resistance of the cascode opamp is also too high to matter. So what is left is just a gm loaded by an inductor, giving 90 degree phase lead. Ken Kundert wrote on Nov 24th, 2013, 12:18am:
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Title: Re: phase plot of an amplifier Post by Frank Wiedmann on Nov 26th, 2013, 12:40am aaron_do wrote on Nov 25th, 2013, 4:20am:
saying a signal that never changes in time has a phase is debatable...anyway you've been doing this longer than me and you have a nice website...so I'll just concede the point :P[/quote] Philosophical discussions aside, this is the generally used notation (for example in S-parameter files). |
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