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Design >> Mixed-Signal Design >> pipelined ADC MDAC
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Message started by aaron_do on Dec 8^th, 2013, 9:44pm

Title: pipelined ADC MDAC
Post by aaron_do on Dec 8^th, 2013, 9:44pm

Hi all,

for pipelined ADC MDAC, in the hold phase, the DAC output is subtracted from the input. My question is how do you drive the DAC output? It seems like it requires an opamp with requirements very similar to the actual MDAC. Any thoughts on this?

For instance, it needs to be able to drive the capacitors used in the MDAC, with low noise, and a high resolution representation of the DAC output (actually this last requirement I think depends on part 2 of my question below).

Part 2 of my question is, if you do need an opamp to drive the MDAC output, do we just have one opamp for all stages to share? This seems likely to me, otherwise each individual opamp would need to act precisely the same.

thanks,
Aaron

Title: Re: pipelined ADC MDAC
Post by carlgrace on Dec 25^th, 2013, 8:53pm

Hi Aaron,

Typically in an MDAC there is no explicit DAC circuit. The "DAC" is simply the differential reference circuit and some switches. That's why the circuit is called an "MDAC" or multiplying digital-to-analog converter. Essentially, in the acquisition phase, the MDAC capacitors are pre-charged to the output of the previous stage. Then, depending on the sub-ADC code, the DAC is connected as +Vref, 0, or -Vref (in the case of a 1.5b stage).

You don't need a high resolution DAC (only needs to be the same as the number of bits per stage). What you need is high DAC linearity. This is why the 1.5b/stage topology is popular: a three-level DAC is inherently linear in a differential sense.

So the answer is, no you don't need an opamp to drive the DAC output. Now you DO typically need a reference buffer to drive Vref and -Vref but this is shared for the whole converter. THe specs on the reference buffer depend on the speed and accuracy of the ADC and the amount of capacitance it drives.

Title: Re: pipelined ADC MDAC
Post by aaron_do on Jan 2^nd, 2014, 6:13pm

Hi carlgrace,

I've been reading over all your replies and they're very helpful. Some of them I had kind of already figured out (like the fact that the S/H is unavoidable), and some I'm still thinking about (like why redundancy may not help so much at higher frequencies).

For this particular question, I was actually referring to the reference buffer but I worded my question poorly.

thanks,
Aaron

Title: Re: pipelined ADC MDAC
Post by carlgrace on Jan 6^th, 2014, 9:38am

The reference buffer is a very important part of the design! Typically it needs to settle to about N-1 bits of accuracy for an N-bit pipeline before it starts to limit your performance.