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Design >> RF Design >> NFmin is very low. Is it normal?
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Message started by baab on Dec 16^th, 2013, 6:52am

Title: NFmin is very low. Is it normal?
Post by baab on Dec 16^th, 2013, 6:52am

Hi,
I am simulating cascode LNA in cadence. Below is my schematic with the operating frequency fc=1.555GHz. For the first time, I want to run for Gmax and NFmin. All parameters I set as in the picture. What I am confusing is about NFmin. As you can see in the picture, NFmin is very very small. It is about 106mdB while Gmax also relatively high, Gmax=35.5dB.
I know that NFmin here is what we can get if good noise matching is ensured. But because its value is too low and seem very good! That is abnormal.
Could you please tell me about this? Is there something wrong with my simlation?
Is it good to have very low NFmin like that?

Title: Re: NFmin is very low. Is it normal?
Post by baab on Dec 16^th, 2013, 6:54am

Here is the Gmax and NFmin pictures. Sorry for the inconvinence. I can't attach two pictures in only one post.

Title: Re: NFmin is very low. Is it normal?
Post by baab on Jan 7^th, 2014, 1:59am

I just figured out why the NF is so low. It is because all my components are ideal. The inductors and capacitors are ideal and thefore the noise is only from resistors and two transistors.
In TSMC 0.13um how can I know the internal resistance in each inductor?

Title: Re: NFmin is very low. Is it normal?
Post by aaron_do on Jan 7^th, 2014, 6:22am

Quote:

how can I know the internal resistance in each inductor?

The resistance depends on how you model your inductor. The simplest model you could assume would be just a series inductor and a series resistor. In such a case you could simply do a DC simulation to check the resistance. Try reading up on inductor modeling for more complicated models. Also, its a good idea to design your own inductors if you want the best performance.

Aaron

Title: Re: NFmin is very low. Is it normal?
Post by baab on Jan 17^th, 2014, 10:25pm

Hi, can you explain why R = 1k is put there?
Is it used to create a filter together with L = 1H?

Title: Re: NFmin is very low. Is it normal?
Post by aaron_do on Jan 18^th, 2014, 7:56pm

Hi,

I'm not really sure why the 1kohm resistor is there. I don't think it would have much effect on the frequency response. It might make some sense if you were using practical inductor and capacitor values.

By the way, regarding your NFmin, I haven't seen NFmin that low even for just a single transistor, but I haven't really checked for the more advanced processes. You might want to check the value with theoretical equations just to see if its in the ball park.

cheers,
Aaron

just realised you're using 0.13um technology, so its not that advanced. I didn't know NFmin could be that low...

Title: Re: NFmin is very low. Is it normal?
Post by baab on Jan 19^th, 2014, 1:59am

Thank you, Aaron.

I am following a tutorial about LNA and that circuit is from there together with the resistance R = 1k.

I thought that it will be part of a band-pass filter.

Code:

By the way, regarding your NFmin, I haven't seen NFmin that low even for just a single transistor, but I haven't really checked for the more advanced processes. You might want to check the value with theoretical equations just to see if its in the ball park.

Haha, it is my mistake. In that circuit, only TWO transistors are from TSMC 0.13 and the rest are from Analoglib (standard).

I tried to replace all components by the ones in TSMC 0.13 but NFmin is really VERY high. I want to get NFmin < 2dB but in the simulation, it is always larger than 13dB. Could you tell me your opinion?
How can I get NFmin < 2dB with TSMC 0.13? I am at lost as all components from the library cause noise for the entire circuit.
Also as I know, NFmin doesn't depend on the width of transistors therefore I didn't change them.

Title: Re: NFmin is very low. Is it normal?
Post by aaron_do on Jan 19^th, 2014, 6:46am

Hi baab,

I don't understand what mistake you made in the first place. If you are only trying to find the NFmin of the two transistors, then it is OK to use all other components from analogLib. If you want to use components from TSMC's PDK, then there's no way you can get 1 F capacitors and 1 H inductors. Large values will not substitute well either as parasitic resistance and capacitance will affect their performance. In other words, just use ideal components from analogLib for the simulation of NFmin. If you want to take into account inductor Q, then just assume a reasonable value and add in some resistance.

As for the device width, it might make some difference to the NFmin if the 1kohm resistor comes into play. I would just remove it if I were you as I still can't really figure out what its for. I'm pretty sure it is not part of any filter.

regards,
Aaron

Title: Re: NFmin is very low. Is it normal?
Post by baab on Jan 19^th, 2014, 9:03am

Hi,

Quote:

I don't understand what mistake you made in the first place.

I simulated to get NFmin with components as follows.

Two transistors: rfnmos 2V: TSMC 0.13um
Resistors, inductors, capacitors: analogLib

and the result is that NFmin is very low. It is about 0.125dB.

I read somewhere that to get NF < 2dB is not easy but as in the result NFmin = 0.125dB is incredibly small. I know the difference between NF and NFmin but with noise matching we can turn NF to NFmin, right?

Quote:

If you want to use components from TSMC's PDK, then there's no way you can get 1 F capacitors and 1 H inductors.

Yes, I tried that but really impossible.

Quote:

In other words, just use ideal components from analogLib for the simulation of NFmin.

I am wondering why. NFmin is calculated for entire the circuit. And if so, it will depend on Ls, Lg, R..., right?

And when we say that the chip using 0.13um technology, do we mean that all components have to be from TSMC 0.13um?

Title: Re: NFmin is very low. Is it normal?
Post by aaron_do on Jan 19^th, 2014, 5:07pm

Hi baab,

Quote:

This is the correct method if you want to the absolute lowest possible NF. In the end, you will have to take into account inductor Q.

Quote:

I read somewhere that to get NF < 2dB

Its very difficult if you are using on-chip inductors. If you are using off-chip inductors, it is possible to get NF lower than 1 dB even in CMOS. The two big contributors to the LNA NF are the transistors, and the inductors.

Quote:

Yes, I tried that but really impossible.

Actually there is no point in trying because the results won't make any sense at all. As I mentioned, your inductors play a critical role in the noise performance, and very large inductors typically can't get very good Q. There is some optimal inductor size which will give you the best Q.

Also, if minimum possible NF is really your goal, then you must design your own inductors. It is possible to get significantly better Q by designing your own inductors. Also, if you can make use of bondwire inductance, it also has much better Q than typically found on-chip (its usually limited to around 1-2 nH).

You should also know that any trace of appreciable length will contribute inductance. For example, your PDK's inductor has the position of its terminal defined. But for your design, you might need to run a trace just to reach that terminal. This will contribute inductance, and so it should be taken into account. It really depends on your design though. This is mainly true for high frequency or high power designs.

Quote:

And when we say that the chip using 0.13um technology, do we mean that all components have to be from TSMC 0.13um?

You must follow the DRC rules (for the most part). That means you can design your own inductors (good idea), capacitors (not always necessary), and even transistors (sometimes people use special layouts for specific applications like high-power designs).

However, in the context of NFmin, you are better off using capacitors and inductors from analogLib, and then adding some parasitic resistance. For example, suppose you need a series inductor, Lg, at the gate. You might assume that it will be about 5 nH at 2 GHz, or 63j ohms. You can then assume a Q of 10. This would put your series resistance at 6.3 ohm. Now simulate your NFmin with a 6.3ohm resistor in series with the gate (don't add any inductance, Lg). Based on your noise plot, your simulation will tell you the actual inductance you need; maybe 70j ohm. Then you can re-calculate the series resistance and repeat the process. Since the resistance depends on the inductance you need, it will be an iterative process.

BTW, L1 in your figure can be substituted with a large resistor (10k for example). L2 may not have much effect on your NF, so it can be considered last.

hope it helps,
Aaron

Title: Re: NFmin is very low. Is it normal?
Post by baab on Jan 19^th, 2014, 7:34pm

Thank you for your insight, it was very helpful.

Quote:

This is the correct method if you want to the absolute lowest possible NF. In the end, you will have to take into account inductor Q.

As you said, I need to take inductor Q into account by using a resistor and an inductor from analogLib.
What is the difference between the inductor got from this (including the ideal resistor and ideal inductor) and the inductor from TSMC 0.13?
I suppose that they have the same series inductance and resistance.

Quote:

I see.

Quote:

When you said design, do you mean that I need to change dimensions such as width, number of turns, ... to get optimum value?

Quote:

I remember that somewhere but I can't figure out why. Could you explain why off-chip inductors give a better NFmin?

Quote:

However, in the context of NFmin, you are better off using capacitors and inductors from analogLib, and then adding some parasitic resistance. For example, suppose you need a series inductor, Lg, at the gate. You might assume that it will be about 5 nH at 2 GHz, or 63j ohms. You can then assume a Q of 10. This would put your series resistance at 6.3 ohm. Now simulate your NFmin with a 6.3ohm resistor in series with the gate (don't add any inductance, Lg). Based on your noise plot, your simulation will tell you the actual inductance you need; maybe 70j ohm. Then you can re-calculate the series resistance and repeat the process. Since the resistance depends on the inductance you need, it will be an iterative process.

I'd like to ask some questions.
1. Because all inductors are not ideal. They have internal resistance. If so, is my initial plot NFmin with the circuit using ideal inductors (from analogLib) and Q = infinity useless?
I feel that because after all we replace all the ideal inductors with other inductors with Q taken into account. And now NFmin will change, not the one before.

2. You said "don't add any inductance, Lg", I am wondering why. Does NFmin depend on Lg, Ls? Assuming that they are ideal (without internal resistance).

Sorry for asking a lot of questions. I can't ask anyone else in my place. Your help and books are what I can find!

I will sum up what I have to do step by step and hope you could help me check if that is OK.

Title: Re: NFmin is very low. Is it normal?
Post by aaron_do on Jan 19^th, 2014, 11:44pm

Hi baab,

I think my explanation was a bit unclear.

Quote:

As you said, I need to take inductor Q into account by using a resistor and an inductor from analogLib.

This is the main point that you misread. If you are simply looking for NFmin, you don't need to add any inductance at all. You only need to add the equivalent parasitic resistance of the inductor. By definition, the inductance (the imaginary impedance) itself will not have any impact on NFmin. However, you need to make an assumption about what is the parasitic resistance to use based on how much inductance you intend to add. So if you think about it, its an iterative process.

Quote:

When you said design, do you mean that I need to change dimensions such as width, number of turns, ... to get optimum value?

Yes. You can try multiple metal layers, different widths for the inner turns, and you could even try different shapes to fit your design area better.

Quote:

I remember that somewhere but I can't figure out why. Could you explain why off-chip inductors give a better NFmin?

They are made using much wider metal so they have less series resistance.

Quote:

1. Because all inductors are not ideal. They have internal resistance. If so, is my initial plot NFmin with the circuit using ideal inductors (from analogLib) and Q = infinity useless?

As I explained above, an inductor's impedance can be written as R + jX. The value X has no impact on NFmin. So you only need to include R in the simulation of NFmin. You could also do a post-layout simulation of the transistor since the transistor's layout will affect NFmin. After you have found the ideal value for the inductance, you can try and design it with the best possible Q.

Using ideal inductors just lets you know how good or bad your inductors are when you include them later.

Quote:

You said "don't add any inductance, Lg", I am wondering why. Does NFmin depend on Lg, Ls? Assuming that they are ideal (without internal resistance).

I guess I answered this already.

hope it helps,
Aaron

EDIT:
btw, I believe the 1kohm resistor was just to model the noise from the load inductor.

Title: Re: NFmin is very low. Is it normal?
Post by baab on Jan 20^th, 2014, 12:21am

Hi again, Aaron.

Please check if I understand you correctly.
I need to read it many times but here is just what I understand right now.

Quote:

As I understand, ideal inductor will not cause thermal noise at all. I think this is what you meant in "By definition".

However, my confusion is from the input referred noise sources, Vn and In.
For example, Vn and In, at the input in the application note:
http://www.maximintegrated.com/app-notes/index.mvp/id/3169
(Please see this part:
Figure 3. Again, a noisy, two-port network can be represented as a noise-free, two-port network with external noise sources Vn and In at the input.)

Although, ideal Ls and Lg (let assume that Q = infinity for now) don't introduce any noise to the circuit but the input referred noise sources, Vn and In, will depend on the values of them.
I mean that Vn and In are functions of Ls and Lg.
And NF is a function of Vn, In.
In the end NF will depend on Vn and In. Or NFmin also depend on Vn and In.

In other words, NFmin will depend on Ls and Lg.

I guess I am wrong somewhere. Please let me know. BTW, if you had any proof that NFmin doesn't depend on Ls, Lg, please tell me. I really want to read it.

Now, I think I understood what you meant. Here is what I got so far. I will put it all here. Hope you could check and guide me if I am going astray.

Step 1:
First, I need to run NFmin by sweeping Vgs. From the NFmin plot, I need to choose the value of Vgs that satisfies the specification (for example, NF < 2dB).

Actually, I run it and NFmin is very low in a wide range of Vgs. It looks like that NFmin almost no depends on Vgs. (for example, with NFmin plot in post #2, you can see that NFmin almost constant for a range of Vgs from 0.5 - 0.8V)
Then what criteria should I consider here to pick one Vgs?

I think it is about power consumption. The larger Vgs, the large power consumption.

Step 2:

I need to do power matching.

(gm*Ls)/Cgs = Rs

and operating frequency:

fo = 1/(2*pi*sqrt(Cgs(Ls + Lg))

From step 1, I chose and fixed Vgs. For example, I chose Vgs = 0.7V.
Then I run DC analysis and find operating point of transistors.

From that I get necessary values such as:
gm: transconductance of common source transistor
Cgs: from DC operating point, I got Cgg = Cgs + Cgb + ...
And with given Rs = 50 Ohms, I can infer the value for Ls.

Ls =(Rs*Cgs)/gm.

Similarly, from operating frequency formula, I can infer the value of Lg.

Now I have ideal values Ls, Lg.

Step 3. Take inductor Q into account.

With Ls, Lg got above, by some way ( I think based on my operating frequency) I need to find the resistances associated with them.

For example:

With Ls: I got R1 (I chose R1 because the name Rs is dedicated to source resistance)

With Lg: I got Rg.

Now, put R1, Rg into the circuit. No need to add inductance part at all and re-plot NFmin.

From NFmin, I need to consider if it meet my specification. IF not, change R1, Rg ( this also means Ls, Lg will change) and check again.
Do this step until requirements are met.

Quote:

EDIT:
btw, I believe the 1kohm resistor was just to model the noise from the load inductor.

Well, I think you are right. I have just seen another LNA circuit in which
the drain is Rp//Lp//Cp.

Title: Re: NFmin is very low. Is it normal?
Post by aaron_do on Jan 20^th, 2014, 3:55am

Hi baab,

I think for the most part you are getting it. Lg doesn't affect NFmin since Lg is at the input. Ls might affect NFmin. I can't really remember, so you would have to do some analysis. If it is at the input, it won't affect NFmin. If it is after a lot of gain, it will have little effect on NFmin.

As for Vgs, its a tradeoff. It affects linearity, power consumption, and fT. In fact, if noise and gain are your only considerations, a low overdrive voltage can actually be better in some circumstances.

regards,
Aaron

Title: Re: NFmin is very low. Is it normal?
Post by baab on Jan 20^th, 2014, 8:38am

Thank you again!

I want to ask some more questions.

1. After I get the values of Ls and Lg, how can I know the resistance associated with them?

My thought now is that I need to simulate quality factor Q of an inductor in TSMC 0.13um and then calculate parasitic resistance from that Q.

2. Where I need to use Noise circle analysis? At present, I am reading about them but I still not really sure.
I know that if we get noise matching the noise circle will be a point.
And btw, how can we know Zopt?

Here is my opinion.
I will do sp analysis. From that we need to will plot noise circuit with sweeping variable is noise level.

For example, my NFmin is about 1.5dB
then I will sweep NF from 1.5dB to 1.8dB.

With 1.5dB, the noise circle will be a point not a circuit and I will read out the optimum impedance from that point.

Is that correct?

Title: Re: NFmin is very low. Is it normal?
Post by aaron_do on Jan 20^th, 2014, 5:45pm

Hi baab,

its been a while since I read about all of that...

Quote:

My thought now is that I need to simulate quality factor Q of an inductor in TSMC 0.13um and then calculate parasitic resistance from that Q.

You can just assume a typical value for the Q factor (10 for example), and use that to find NFmin. Remember, its iterative. So step one you assume say 5 nH and based on Q = 10 you know the resistance. Then assume your noise circle gives you the optimum L of 6 nH. So you would recalculate R based on 6 nH and Q = 10, and then find the new optimum value. Suppose it is 5.8 nH. You then recalculate R for 5.8 nH and Q = 10, and so on and so forth...

Quote:

2. Where I need to use Noise circle analysis? At present, I am reading about them but I still not really sure.

I don't remember too well what exactly the noise circle plots, but I don't know how you can sweep NF from 1.5 dB to 1.8 dB. I'm guessing the noise circle plots lines of constant NF, and you need to chose the line with the lowest NF? Maybe somebody else can answer this...

I think its all discussed very well in RF Circuit Design by Chris Bowick.

regards,
Aaron

Title: Re: NFmin is very low. Is it normal?
Post by baab on Jan 21^st, 2014, 3:45pm

Thank you.
I think in the end I will have to replace real inductors (inductors from TSMC 0.13um) and simulate again. Is that right?

I mean that at first, for the simplicity sake we replaced real inductors by an ideal inductor and ideal resistor in series. However, when all things complete, we need to use real model, pick inductors from TSMC 0.13um that have almost the same parameters such as inductance and internal resistance.

Title: Re: NFmin is very low. Is it normal?
Post by aaron_do on Jan 21^st, 2014, 4:56pm

Sure. In the end you can use real components just to see if you really achieved NFmin. But for the initial simulations, you don't need to include any Lg at all since NFmin will calculate based on the best case input matching network.

regards,
Aaron

Title: Re: NFmin is very low. Is it normal?
Post by baab on Jan 23^rd, 2014, 5:09pm

Hi,

I run Gmax and NFmin with Vgs to choose bias voltage. I have just seen another method is to plot gm, gd0, Vgs as functions of current density Id/W. And from that choose optimum drain current density for minimum NF.

Is there any difference between two methods? I see that the first one is much more simple but don't know if there is any problem with it?

Title: Re: NFmin is very low. Is it normal?
Post by aaron_do on Jan 24^th, 2014, 1:32am

I'm not really sure I understand your second method. So you're saying to fix the width, and plot gm versus Id, gd0 versus Id, and Vgs versus Id? And then what? NFmin versus Id? In the first place it seems like there's a lot of redundant data there...

I guess there's only a problem if you don't really reach NFmin...

regards,
Aaron

Title: Re: NFmin is very low. Is it normal?
Post by baab on Jan 24^th, 2014, 4:45am

Hi,

Could you take a look at the procedure to design a LNA at near the end of the page?
http://www.ece.ucsb.edu/yuegroup/Teaching/ECE219Winter2013/Lecture%20slides%20and%20notes/ECE219-Lec3-4-notes-LNA.pdf

The second method that I said in in step 3.

"For a minimum channel-length device, plot (by simulation or otherwise) gm, gd0, and VGS as functions of current density ID/W"

Title: Re: NFmin is very low. Is it normal?
Post by aaron_do on Jan 24^th, 2014, 7:56am

I took a quick look at it, and it doesn't tell you which operating point to pick for minimum NF. It simply tells you to plot gm, gd0 etc, and then pick a biasing point. So I don't see how you can use this method to get minimum NF. It is useful anyway if you want to see the tradeoff between NF and IIP3.

Title: Re: NFmin is very low. Is it normal?
Post by baab on Feb 19^th, 2014, 6:16pm

I'd like to ask another question about minimum noise figure NFmin. As far as I know, NFmin depends only on the geometry of the two transistors. For my example, NFmin will change as dimensions L and W change. This is where I get confused about the procedure to design LNA.
As in the procedure, first we simulate NFmin vs Vgs (bias voltage). From that we can choose Vgs that sastifies NF requirement.
After fixing Vgs, we scale W and L of transistors to get NFmin. This is where the problem is.

For example, initilally, we set W1 and L1 for transistors to simulate NFmin vs Vgs.
From the plot of NFmin vs Vgs, we choose Vgs and fix it.

After fixing Vgs, we scale W1 and L1 to W2 and L2 respectively to get NFmin. However, when W and L are set to W2 and L2, NFmin will be changed. It is no longer the initial NFmin that we choose above.

Finally, what is the point of simulating NFmin here?
Thank you.

Title: Re: NFmin is very low. Is it normal?
Post by aaron_do on Feb 19^th, 2014, 9:06pm

Hi baab,

really I think your design is going to start with a power consumption budget. Based on this budget, you can sweep Vgs and W to get NFmin. However, if you really want the minimum possible NF, its not that straightforward as there are a lot more factors involved. For example, different transistor sizes will require different inductor sizes. And depending on the layout constraints, they will have different Q factors which will lead to different NF. You also need to take into account the NF of the following stages. So your gain will become important too.

I suggest that you keep NFmin in mind, but start studying other things first so you can get a feel for the different considerations that come into play. For example, inductor modeling and design will be very important.

regards,
Aaron

Title: Re: NFmin is very low. Is it normal?
Post by baab on Feb 20^th, 2014, 8:48pm

Hi, Aaron.

I would like to ask a question. My input is matched. Z11 = 50 Ohms with Real{Z11} = 50 Ohms and Im{Z11} = 0.01Ohms.
However, I checked S11 and it it still large (about -6dB). Could you explain why?

Title: Re: NFmin is very low. Is it normal?
Post by aaron_do on Feb 20^th, 2014, 10:33pm

Hi baab,

that's quite odd. Are you running a 2-port simulation or 1 port? If you are running a 2-port simulation, can you try just running a 1-port simulation and see if this still happens? In theory it could happen, but its unlikely if S12 is good...also, maybe you could attach your results.

regards,
Aaron

Title: Re: NFmin is very low. Is it normal?
Post by baab on Feb 20^th, 2014, 11:34pm

Thank you, Aaron. I used two ports.
I will try your solution now. BTW, I made a new thread for this topic with some more information.

Title: Re: NFmin is very low. Is it normal?
Post by baab on Feb 21^st, 2014, 12:21am

Well, Aaron. I tried it by unconnecting output port. This means that my output LNA isn't connected to anything else.
Ha, S11 is really good now! At my frequency it is about -59dB. That is great. Could you explain the reason?

Title: Re: NFmin is very low. Is it normal?
Post by aaron_do on Feb 21^st, 2014, 1:07am

Hi baab,

obviously I haven't seen your schematic, but I guess that S12 is very poor. If you want to know more about s-parameters, you should read that book I mentioned before, "RF Circuit Design" by Chris Bowick.

To give you a watered down explanation, you can say that S11 is defined when the load is equal to 50 ohm (again this isn't exactly true and you need to read to understand more). On the other hand, Z11 is defined when the load is an open circuit. So that's why you're getting different answers. If S12 is very good, then it won't make much difference whether you look at S11 or Z11.

You should try and improve S12 maybe by using a cascode transistor for example.

regards,
Aaron

Title: Re: NFmin is very low. Is it normal?
Post by baab on Feb 21^st, 2014, 1:40am

Thank you.

I am still reading the book.
I used the cascode topology. I posted the circuit in the new thread here:
http://www.designers-guide.org/Forum/YaBB.pl?num=1392967942

When the output port is not connected, there is not much difference as looking at S11 and Z11.
My S12 is almost constant. It is about -6.4kdB.
It it very good, right?

Title: Re: NFmin is very low. Is it normal?
Post by aaron_do on Feb 21^st, 2014, 3:45pm

if the output port is not connected, S12 is meaningless. What is S12 when the output port is connected?

Title: Re: NFmin is very low. Is it normal?
Post by baab on Feb 21^st, 2014, 6:33pm

Hi, Aaron.

S11 = -36 dB as output port is connected. I think it is good. However, now S11 is about -6dB.

I used cascode topology. Therefore, I think S12 is not problem now.
Could you check the method to choose Ls and Lg that I did here?
http://www.designers-guide.org/Forum/YaBB.pl?num=1392967942

Is it the right way for input impedance matching?