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Design >> Analog Design >> Problems on Current Bias
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Message started by Hao on Jan 20^th, 2014, 4:03pm

Title: Problems on Current Bias
Post by Hao on Jan 20^th, 2014, 4:03pm

Hey guys, I confront problem during measurement on the following issue. Highly welcome to kindly leave any suggestions, analysis, even guess!

1) Description of the circuit: M1 is part of functional circuit; Pad Vbias and resister R are used to bias M1. M2 is added to generate a current mirror with M1, used as an indicator that DC current of M1 could be controlled accurately.

2) Simulation: M1/M2=10; Vbias=0.55V, Ibias=300uA; Iused=3mA

3)In measurement, there are two problems that I confront, described in 4) and 5)

4) Problem 1: "DC Source 1 (V1)" has to be set as high as 0.75V (expected Vbias=0.55V as mentioned above), to make sure Ibias and Iused reach expected 300uA and 3mA.
Does this indicate that when V1=0.75V, V2 reach simulation value 0.55V? the voltage loss from DC source to the gate of M1 is as high as 0.2V?

5)Problem 2: For every chip, it works fine at first. Then during the measurement, the circuit collapses somehow. Ibias will be as high as several mA, and Iused becomes 0. It seems that M2 breaks down, and V2 drops. However, with multimeter I found Vbias and GROUND are not shorted. So anyone have some clues on what is going on?

6) The technology I am using is IBM 130um. Max gate voltage of M1 and M2 are both as high as 1.6V.

Title: Re: Problems on Current Bias
Post by aaron_do on Jan 20^th, 2014, 5:05pm

Hi,

for problem (4), I assume the voltage at the pin (probe the pin itself) is 0.75 V? You should probably check your layout for weak connections in any wire carrying current, particularly the ground and power lines. Also check if there are any diodes that could be turning on (floating bodies for example), or any possibility of latchup.

During your test do you have any input signal, or is it just DC? For problem 5, you mention the circuit suddenly fails. After that, try sweeping the voltage from 0 to 1 V or so. Does it have a turn-on voltage? Maybe its some diode turning on. Also, if you really have a high VDD while the transistor is on for a long period, you could stress the device (HCI).

regards,
Aaron

Title: Re: Problems on Current Bias
Post by Hao on Jan 27^th, 2014, 8:35am

Hi Aaron,

Thanks a lot for your reply! Your reply give me a lot of hint, I actually have checked my layout carefully. Fortunately I didn't find any especially latchup.

But to update, I finally get a way to prevent the chip from keeping breaking down, that is, put a current-limiting resistor in series, between DC source and pad of Ibias. So I guess, the chip breaking down might because an ESD event or something.

As for the voltage at the pin, I don't pay attention on it anymore. instead, I only concern bias current. once bias current reached expected value, the total current from voltage supply reach the expected value too. But, I will keep trying to find the reason for problem (4), because it is still a issue in future bias circuit.

Thank you!

Regards :)
Hao

aaron_do wrote on Jan 20^th, 2014, 5:05pm: