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Design >> Mixed-Signal Design >> ADC Unit Capacitance
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Message started by aaron_do on Jan 26^th, 2014, 5:34pm

Title: ADC Unit Capacitance
Post by aaron_do on Jan 26^th, 2014, 5:34pm

Hi all,

just wondering, is it practical to have a very small unit capacitance? I am working on a SAR ADC, and while the minimum unit cap in the PDK is about 1.7 fF, it would be better if I could have something even smaller. However, with all the parasitic cap around, I'm wondering if its a bad idea. I've done some simulations, and the parasitic capacitance at the comparator node doesn't seem to affect the SFDR even when its mismatched. However, I haven't simulated any input cap non-linearity. So if the comparator node's capacitance changes with the input signal then I might be in trouble...

Also, I know its possible to add a series cap in the DAC array, but this would degrade the linearity, so I want to avoid that if possible.

Any input is welcome.

thanks,
Aaron

Title: Re: ADC Unit Capacitance
Post by RobG on Jan 27^th, 2014, 8:39am

Wow, that is a small cap. Usually the cap-DAC isn't realized using super small capacitors for the LSB. Instead it is done by splitting the cap dac with a series capacitor. I'd be more worried about noise coupling into the node than mismatch, since mismatch of the LSB can be quite large (~ 50%).

Title: Re: ADC Unit Capacitance
Post by aaron_do on Jan 27^th, 2014, 4:52pm

Hi RobG,

thanks for the reply. Yeah I'm aware of splitting the cap DAC, but this degrades the linearity. So I want to avoid it if possible. I ran monte carlo simulations on the cap mismatch alone and it seems good enough. Not sure about noise coupling though...I guess its one more thing I will have to think about.

So do you have an opinion on the minimum capacitance size that should be used?

thanks,
Aaron

Title: Re: ADC Unit Capacitance
Post by loose-electron on Jan 27^th, 2014, 5:07pm

Time to refresh your memory on KT/C noise.

Title: Re: ADC Unit Capacitance
Post by aaron_do on Jan 27^th, 2014, 5:31pm

Hi loose-electron,

I'll have another look, but I don't think its a bottleneck for my particular implementation. I'm just wondering if there's anything else stopping me from using such a small capacitor. Just for a quick check...

assume 12 bit with 1-V reference, LSB²/12 = 5n V²

kT/C = 5n => C = 0.8pF, so LSB cap = 0.8 pF/2¹² = 0.2 fF.

Have I made a mistake somewhere?

thanks,
Aaron

Title: Re: ADC Unit Capacitance
Post by boe on Jan 28^th, 2014, 2:06am

Aaron,
C=0.2fF => kT/C = 20u V² for the LSB cap.
Also remember that charge injection is highly critical on so small a cap.
- B O E

Title: Re: ADC Unit Capacitance
Post by aaron_do on Jan 28^th, 2014, 4:58pm

Hi boe,

thanks for the tip about the charge injection.

I don't really get your point on the kT/C noise though. Are you implying that the LSB cap needs to be large enough so that its kT/C noise is less than the quantization noise? If so, I think I would disagree since in a SAR ADC, the sample and hold is performed on all of the caps together.

Aaron

Title: Re: ADC Unit Capacitance
Post by RobG on Jan 28^th, 2014, 7:09pm

aaron_do wrote on Jan 27^th, 2014, 4:52pm:

So do you have an opinion on the minimum capacitance size that should be used?

I've never ventured below 25 fF so I have no experience to offer. I wouldn't go less than the minimum 1.7 fF cap in the PDK unless you really know the process. I'd think parasitics from your metal lines could easily introduce significant errors - more than using a cap splitter.

The charge and/or noise contribution by the LSB cap is down by 2^-N so I don't think kT/C will matter.

Title: Re: ADC Unit Capacitance
Post by boe on Jan 29^th, 2014, 5:13am

aaron_do wrote on Jan 28^th, 2014, 4:58pm:

Aaron, you are right regarding kT/C noise - I was a bit too fast on that one.
- B O E

Title: Re: ADC Unit Capacitance
Post by aaron_do on Jan 29^th, 2014, 5:04pm

Quote:

I was a bit too fast on that one.

Happens to us all.

BTW, I just finished reading "A 1.7 mW 11b 250 MS/s 2-Times Interleaved Fully Dynamic Pipelined SAR ADC in 40 nm Digital CMOS", which was written by some researchers from IMEC. On page 2, quote, "the total size of the fine SAR DAC capacitance is 62 fF, limited by the size of a unit capacitance". Given that its a 7b SAR, I read that to mean that the unit capacitance is 62/(2*2^7) = 0.24 fF. However, the picture indicates the biggest capacitor is a 16x unit cap (doesn't make much sense to me since that wouldn't be 7b), and that would put the unit capacitance at roughly 1 fF.

So apparently it is possible to use very very small capacitors...

regards,
Aaron

Title: Re: ADC Unit Capacitance
Post by carlgrace on Jan 30^th, 2014, 10:09am

A super small unit cap might be ok for a research project but I would be cautious using one for a production part.

I tried using really small unit caps on a converter a few years ago (noise spec was relaxed) and ended up getting much worse matching than estimated by monte carlo. If you're using MIMs for best matching you need to be close to where the foundry actually measured data. Extrapolation is dangerous. If you're using fringe caps calibration is mandatory since most foundries don't track that.

Title: Re: ADC Unit Capacitance
Post by loose-electron on Jan 30^th, 2014, 10:20am

Generally your minimum capacitance size will be driven by a bunch of things:

kT/C noise
Charge injection of switches
Matching accuracy
Interconnect parasitics
Perimeter parasitics (for smaller device they are a bigger part of the total)
Foundry limitations

Did I forget anything?

Title: Re: ADC Unit Capacitance
Post by RobG on Jan 30^th, 2014, 10:50am

loose-electron wrote on Jan 30^th, 2014, 10:20am:

Your desire to keep your job :). I've learned to use my cleverness to decrease risk, not to do something merely because it is more clever than before. Unless it is a really cool idea of course.

Title: Re: ADC Unit Capacitance
Post by aaron_do on Jan 31^st, 2014, 5:51am

Actually if i dont use a very small cap, then i probably need a bridge cap (its a SAR). Based on my simulations, the ADC linearity is degraded enough using the bridge cap that it would mandate calibration even in the nominal case. So my motivation for using such a small cap is to have some confidence that the design will work even if the calibration has issues. Now im a little worried its gonna backfire...anyway i will figure something out.

Thanks,
Aaron

Title: Re: ADC Unit Capacitance
Post by carlgrace on Mar 7^th, 2014, 8:44pm

RobG wrote on Jan 30^th, 2014, 10:50am:

I've learned to use my cleverness to decrease risk, not to do something merely because it is more clever than before. Unless it is a really cool idea of course.

This is some of the best advice I've seen in a long time. I think focusing on risk and being very nervous about being "clever" is a sign of a mature designer. There's a reason almost all of my Pipelined ADCs use 1.5 bits/stage.