The Designer's Guide Community Forum

The Designer's Guide Community Forum
https://designers-guide.org/forum/YaBB.pl
Design >> Analog Design >> Regulator closed loop bandwidth doubt
https://designers-guide.org/forum/YaBB.pl?num=1390963130

Message started by analog geek on Jan 28^th, 2014, 6:38pm

Title: Regulator closed loop bandwidth doubt
Post by analog geek on Jan 28^th, 2014, 6:38pm

Hello Folks,
SO I am working on LDO for high frequency devices like PLL. I have some doubts regarding some terminologies which are pretty much easy.

1. So there are two devices which will decide bandwidth of the regulator those are output PMOS device and amplifier. In my case output device (PMOSFET) has the dominant pole frequency while amplifier has very high frequency pole. So we can say that regulators gain start dropping after dominant pole of the output devices (PMOSFET). So how can we define the bandwidth of the regulator??...Is the bandwidth of the regulator means the frequency at which gain of the regulator start rolling off because of low dominant pole at the output?...what will decide bandwidth of the regulator, PMOS device or high bandwidth amplifier??..

2. Also there will be negative feedback used in the amplifier for stability which will increase the bandwidth and decrease the gain. How is this closed loop bandwidth of the amplifier related to bandwidth of the regulator?....

Basically having confusion between closed loop regulator bandwidth, effective amplifier bandwidth????