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The Designer's Guide Community Forum
https://designers-guide.org/forum/YaBB.pl Design >> Mixed-Signal Design >> SAR ADC decoupling capacitance https://designers-guide.org/forum/YaBB.pl?num=1390989968 Message started by aaron_do on Jan 29th, 2014, 2:06am |
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Title: SAR ADC decoupling capacitance Post by aaron_do on Jan 29th, 2014, 2:06am Hi all, I've noticed that not many papers talk about the decoupling capacitance requirements of a relatively high-speed (say 100 MS/s) high-resolution (>10 b) SAR ADC. However, based on my simulations, the amount of decoupling capacitance required for the reference voltages could be up to 1 nF. I've also noticed from the micrographs that there's a conspicuous amount of die area not part of the "core area" in some of these designs. For instance, one paper I recently read had at least 0.5 mm2 of unlabeled die area. With about 3fF/um2 that could translate to 1.5 nF of decoupling capacitance. So part 1 of my question is, is such a large capacitance practical? Part 2 is, since its decoupling cap, is there any issue with combining MOM and MOS caps? thanks, Aaron |
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Title: Re: SAR ADC decoupling capacitance Post by carlgrace on Jan 30th, 2014, 10:16am Question 2: No problem (probably). People put MIMs on top of MOS caps all the time. A few processes don't allow diffusion on MIM so check your design rules. Question 1: 1 nF is probably not practical. There are two schools of thought for ADC reference design. Either a) you make the reference super-duper low impedance so that the delta-q from the ADC isn't enough to move the reference more than an LSB/2. Or, b) you can make a fast reference buffer that recovers before the next sampling event. Typically people use a) if they can put the decoupling (or at least most of it) off chip. Beware the bondwire inductance if you do this. People typically use b) when they need an internal reference decoupling. The downside is you need to design a fast, low-impedance buffer (typically class A/B). You can spec out your buffer by calculating the current it will need to supply to the reference node. Figure out the worst cast delta-Q (based on your reference voltage and your cap sizes) and then use the sampling period (your delta-t) to calculate current requirements (delta i = (delta Q)/(delta t)) Good luck! PS I thought you were working on a pipelined ADC? |
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Title: Re: SAR ADC decoupling capacitance Post by aaron_do on Feb 2nd, 2014, 6:40pm Hi carlgrace, thanks for the help. Well the specs I was given seem like they can be comfortably achieved with a pipelined architecture, but it would be a stretch with a SAR. Looks like we decided to go with the SAR because its lower power, and it can only get better with technology. The biggest issue however seems to be the reference. Why do you think 1 nF is not practical? Is it just a size/cost issue? Or do you think the Q would not be good enough? Looking at the research papers from IMEC, their power consumption is on the order of just a few mW. This doesn't seem achievable with a proper reference buffer. Furthermore, they appear to use bonding wires (not flip chip), so the other option is tons of decoupling... thanks, Aaron EDIT: actually I did a quick calculation for the decoupling cap just based on charge sharing, and it seems 2N times as much decoupling cap. So it might end up much more than 1 nF... |
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Title: Re: SAR ADC decoupling capacitance Post by aaron_do on Feb 3rd, 2014, 12:09am Hi carlgrace, I've done some more analysis, and regarding option a) I came to a weird conclusion regarding the decoupling capacitance. The conclusion is, "if you want to decouple the reference, you need a huge capacitance. If you aren't willing to put that much decoupling capacitance, then its better not to have any decoupling capacitance at all." The reason is that when you add decoupling, the time-constant of the on-chip reference increases. Since it takes longer to settle, you have to make sure the initial spike in the reference voltage is less than 0.5 LSB. I reached this conclusion after simulating a series RLC with a damping factor of 1. I swept the value of the capacitor, and checked how long it takes to settle to within 12b resolution. I'm not sure if this is what you meant by "Typically people use a) if they can put the decoupling (or at least most of it) off chip." The problem with this method is that my circuit would be more sensitive to any other noise... thanks, Aaron |
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Title: Re: SAR ADC decoupling capacitance Post by boe on Feb 3rd, 2014, 1:48am aaron_do wrote on Feb 3rd, 2014, 12:09am:
Quote:
- B O E |
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Title: Re: SAR ADC decoupling capacitance Post by aaron_do on Feb 3rd, 2014, 5:11am thanks! Aaron |
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Title: Re: SAR ADC decoupling capacitance Post by boe on Feb 3rd, 2014, 5:21am Aaron, don't forget the following spikes... - B O E |
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Title: Re: SAR ADC decoupling capacitance Post by carlgrace on Feb 3rd, 2014, 8:33pm Aaron, You're right that not putting enough decoupling capacitance won't help you much. But believe if you don't put any at all you'll be sorry! If you can't (or don't want to) put enough capacitance on the chip, go for method b. People often try to just put a huge cap off chip and forget about it. This sometimes works but if your ADC is fast the bondwires will kill your reference settling. Even though the caps are low impedance the bond wire becomes higher and higher impedance. |
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Title: Re: SAR ADC decoupling capacitance Post by aaron_do on Feb 3rd, 2014, 10:34pm Hi boe and carlgrace, Quote:
I didn't get that. Could you elaborate? thanks Quote:
my reference will be VDD and GND, but what I wanted to do was feed them in through separate bondwires. I re-did my simulations/calculations, and found that I need around 40 nF of capacitance. I assume the problem you are implying is that the huge voltage spikes will couple to nearby lines etc. So that means that there's a tradeoff between the voltage spike, and how fast I can run my circuit. I've included my simulation in the next two posts. Basically the current pulse is adding 1pC of charge each cycle, and I'm seeing what is the effect of different capacitor sizes from 10 pF to 10 nF in a logarithmic sweep. The resistor is sized so that the damping factor is always equal to 1. You can see that the 10 pF cap settles the fastest, and takes roughly 1 ns. Its not obvious, but for the 1 nF capacitor, in 1 ns, the reference only settles to about 9.3-bit accuracy. Perhaps as you say a buffer is the best option. thanks for the help, Aaron |
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Title: Re: SAR ADC decoupling capacitance Post by aaron_do on Feb 3rd, 2014, 10:35pm Here's the schematic |
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Title: Re: SAR ADC decoupling capacitance Post by aaron_do on Feb 3rd, 2014, 10:35pm Here's the simulation results |
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Title: Re: SAR ADC decoupling capacitance Post by boe on Feb 4th, 2014, 5:22am aaron_do wrote on Feb 3rd, 2014, 10:34pm:
I meant that if you do a conversion, there will be more than on spike on Vref: so you may need to look at the settling behavior of Vref wrt. spikes over time with several pulses [or even conversions] (depending on use case [e.g. discontinuous operation], loading vs. drive strength, gain, ...). - B O E |
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