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Design >> Analog Design >> Band gap +LDO transient measurement not in line with simulation
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Message started by Mikay on Feb 4^th, 2014, 12:21pm

Title: Band gap +LDO transient measurement not in line with simulation
Post by Mikay on Feb 4^th, 2014, 12:21pm

I have a good question: The CMOS die includes a LDO with band-gap. This CMOS die has only four pads.(VDD, GND EN, OUT). Full simulation across PVT under different extreme conditions have been verified in Cadence simulation which show the LDO output should be competely stable 0.5us after EN is turned on. However, my test results show it take a 400us to settles completely. The Yellow line is EN and another is the LDO output.

This LDO has 20MHz GBW.

I have checked the power supply line. It is well bypassed by a 10uF capacitor with very small ripple. Does any know why could happen?

Thanks.

-Mikay

Title: Re: Band gap +LDO transient measurement not in line with simulation
Post by aaron_do on Feb 4^th, 2014, 4:49pm

Hi Mikay,

did you take the package model into account? i.e. the bonding wires...

Aaron

Title: Re: Band gap +LDO transient measurement not in line with simulation
Post by Mikay on Feb 5^th, 2014, 6:32am

Hi Aaron,

The bonding wires are modeled by inductance with 0.5nH/mm. Simulation also shows inductance of ~nH has no effect for the transient since the bandwidth is only 20MHz.(Z=2*PI*20MHz*1nH=0.125ohm).

Where does this large time constant(with ~400us) probably come from?Is there any other possible limiting factor?

Thanks,
-Mikay

aaron_do wrote on Feb 4^th, 2014, 4:49pm:

Hi Mikay,

did you take the package model into account? i.e. the bonding wires...

Aaron

Title: Re: Band gap +LDO transient measurement not in line with simulation
Post by boe on Feb 5^th, 2014, 6:58am

Hi Mikay,
you might have a start-up problem with the bandgap/bias current circuit.
- B O E

Title: Re: Band gap +LDO transient measurement not in line with simulation
Post by RobG on Feb 6^th, 2014, 9:38am

One thing that could give you that type of response is having a zero that didn't quite cancel a pole (a doublet). The zero gets you that initial fast jump up close to the desired value, but the error in the pole/zero cancellation gives you the final slow settling.

Cancelling a pole with a zero can look great in simulation, but mismatches can give you the result you are seeing. Maybe you can add an external RC network to bring it back in line.

A classic paper was done by Kamath, Meyer, and Grey 40 years ago. http://ieeexplore.ieee.org/xpl/login.jsp?tp=&arnumber=1050527&url=http%3A%2F%2Fieeexplore.ieee.org%2Fxpls%2Fabs_all.jsp%3Farnumber%3D1050527

Title: Re: Band gap +LDO transient measurement not in line with simulation
Post by Mikay on Feb 6^th, 2014, 11:33am

Hi BOE,

The bias circuit respond very quickly through Monte Carlo simulation. Yes, it may be due to bandgap.

boe wrote on Feb 5^th, 2014, 6:58am:

Hi Mikay,
you might have a start-up problem with the bandgap/bias current circuit.
- B O E

Title: Re: Band gap +LDO transient measurement not in line with simulation
Post by Mikay on Feb 6^th, 2014, 11:49am

Thanks Rob, there may be a in-band doublet in the band gap loop. The loop was not analyzed in detail manually since it's a very complicated architecture. But to ensure a quick loop response, extensive Monte Carlo simulation has been done and all of the simulation results show the band gap starts up very quickly(less than 300ns). Is it possible Monte Carlo simulation could not predict the doublet space(p1-z1) very accurately and thus the far spaced doublet degrade the speed in the end?

RobG wrote on Feb 6^th, 2014, 9:38am:

Title: Re: Band gap +LDO transient measurement not in line with simulation
Post by RobG on Feb 6^th, 2014, 12:19pm

Mikay wrote on Feb 6^th, 2014, 11:49am:

After thinking about it a bit, it would have to be a vary large mismatch or your doublet is at very low frequency to get a time constant in the 400us range. What are you using for the load capacitance? Maybe it has a large ESR (equivalent series resistance), but it seems unlikely to be that large.

Maybe you are getting some feedback via parasitics into your bandgap or opamp that is shutting it down. These can recover slowly if they are biased lightly or have big filter caps on it.

Title: Re: Band gap +LDO transient measurement not in line with simulation
Post by rf-design on Feb 6^th, 2014, 3:30pm

Mikey,

the time constant of settling is in the range of typical thermal responses of the active devices.

Does the device model have thermal time constants?

Could you selective switch thermal effects on/off?

BR

Reiner

Title: Re: Band gap +LDO transient measurement not in line with simulation
Post by aaron_do on Feb 6^th, 2014, 4:50pm

I just noticed your numbers are in microseconds not nanoseconds...Maybe you have some floating node somewhere, and the initial transient spike is coupling to that node forcing a long transient. Why don't you try slowing down the enable signal (give it a longer rise time).

Aaron

Title: Re: Band gap +LDO transient measurement not in line with simulation
Post by boe on Feb 7^th, 2014, 1:55am

Mikay,
did you check the load vs. load model in your simulation?
- B O E

Title: Re: Band gap +LDO transient measurement not in line with simulation
Post by loose-electron on Feb 7^th, 2014, 6:33pm

One lesson to be learned - Never (never!) tape out a new design without having carefully thought about how you are going to be able to get to and individually test out each and every functional block in the system...

Testability and debug should always be a big part of the design.

Title: Re: Band gap +LDO transient measurement not in line with simulation
Post by analog_rf on Mar 7^th, 2014, 1:28am

how are you measuring startup time.I assume once supply is ramped up and stable you are trying to enable the bandgap. Is the bandgap a very low current structure?Are you adding lot of probe capacitance on the measuring node you are bringing out?

Title: Re: Band gap +LDO transient measurement not in line with simulation
Post by Mikay on Mar 20^th, 2014, 7:35am

Thanks for verybody's warm replies. The problem may be the bandgap output has a slow settling because of the thermal. bandgap should be a zero temperature coefficient in the design, however, the simulation model is not accurate and it has a negative slope over temperature. In my next design, some option which can be trimmed for the bandgap should be reserved so that bandgap out will be constant over temperature to eliminate the thermal effect of the bandgap settling.

Mikay

rf-design wrote on Feb 6^th, 2014, 3:30pm:

Title: Re: Band gap +LDO transient measurement not in line with simulation
Post by RobG on Mar 20^th, 2014, 5:56pm

Glad you are zeroing in on the problem - temperature changes seem like a likely suspect given the time constant (good call). Can you vary the load to produce different temperatures and see a difference in the power up transient?

I'm skeptical that a error in the model temp co would cause such a large error - how much of a temperature difference are you predicting as it powers on? What sort of temp co would you need to get your results? Is the change consistent with what you get when you simply change the ambient temperature? Plus why does it come up to the initial value right away only to dip back down? Ask yourself a lot of tough questions before deciding on trim - I would not have guessed that would be the proper solution.

Make sure the bipolars and other matched devices are common centroid - heat gradients will cause an error that can be surprisingly big. You will see different results depending on if you raise the ambient temperature or put a gradient across the chip with power dissipation on one side of the circuit. I'd rule those out before blaming the model.

Also be aware of resistor self heating. Metal line resistance also has a large temp co.

Title: Re: Band gap +LDO transient measurement not in line with simulation
Post by loose-electron on Mar 26^th, 2014, 11:30am

Heating?
I really doubt it.

Look at the time constants of your reference voltage and bandgap.

Also, the diodes in the BG often do not have their capacitance in the model, and if you have small bias current the time constants can be really off.

Title: Re: Band gap +LDO transient measurement not in line with simulation
Post by Lex on Apr 2^nd, 2014, 1:46am

I share skepticism with Jerry..
I have heard many designers excuse themselves with "thermal response, package stress, substrate noise" and other things that are difficult to check, while for most times the problem turned out to be obvious things like low PSRR, poor settling speed or capacitive coupling.

So how did you do the MC verification? How did you define in simulation whether the BGR is settled? Did you simulate long transients as your measurement result? Are all nodes settled in the simulation?

Title: Re: Band gap +LDO transient measurement not in line with simulation
Post by RobG on Apr 2^nd, 2014, 7:17am

Lex wrote on Apr 2^nd, 2014, 1:46am:

I'll add models to that list of things that get blamed when it is really a something in layout, or a heat gradient ;). Whatever you think it is, definitely be skeptical of your hypothesis and verify it thoroughly.

rg

Title: Re: Band gap +LDO transient measurement not in line with simulation
Post by loose-electron on Apr 2^nd, 2014, 5:14pm

http://electronicdesign.com/products/simulation-vs-silicon-avoid-costly-mistakes-accurate-models

give that a read and see if it rings any bells on stuff you left out.

high impedance nodes with unaccounted for capacitance attached to it would be my best guess.

Title: Re: Band gap +LDO transient measurement not in line with simulation
Post by boe on Apr 7^th, 2014, 4:05am

Hi,
I have already seen a circuit with a start-up time of about 10 seconds [sic!] due to charging of a cap with a MOS in sub-threshold region.
- B O E