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Design >> Mixed-Signal Design >> PLL reference spurs, and jitter vs phase noise
https://designers-guide.org/forum/YaBB.pl?num=1392281185

Message started by aaron_do on Feb 13^th, 2014, 12:46am

Title: PLL reference spurs, and jitter vs phase noise
Post by aaron_do on Feb 13^th, 2014, 12:46am

Hi all,

I'm ran a post-layout simulation on my PLL, and found that the reference spurs are really bad (see below). So I was wondering, do these reference spurs have a direct impact on my jitter performance?

I'm calculating my jitter by integrating the DFT. Just wondering whether I need to integrate the entire spectrum. Also, it seems that it takes time for the jitter to "settle" to its final value. And it seems to take a longer time for this settling when I use a smaller bin width. Does that make sense?

One more thing, if you look at the figure, the "phase noise" of the reference spurs is much worse than that of the main tone around the loop bandwidth. Why would that be?

thanks,
Aaron

EDIT: the node I plotted in the picture below is after buffering and long wiring. When I plotted the differential output of the PLL itself, the performance was much better. However, I'm still curious up to what frequency I should integrate the DFT to find the jitter. When I integrate up to 2x fosc I get a number that seems reasonable. But when I integrate beyond this frequency, the number is much higher (because I'm integrating the harmonics), and I'm sure its wrong since it is worse than the pk-pk jitter on the eye diagram.

EDIT2: I found out that I can just plot the jitter from the cadence's calculator, but its higher than what I got by integrating the DFT up to 2x fosc...

Title: Re: PLL reference spurs, and jitter vs phase noise
Post by carlgrace on Feb 23^rd, 2014, 9:04pm

Hi Aaron,

I don't know what algorithm the Spectre calculator uses to calculate jitter, but I can tell you that spurs don't have a huge effect on the jitter. For clock synthesizers the spurs aren't a huge design driver so you can do a simpler charge pump. For RF frequency synthesizers the spurs are everything. It really depends on your application.

Besides, if you're doing an RF PLL you're going to be using an LC oscillator which has much better raw spur performance anyway.

Title: Re: PLL reference spurs, and jitter vs phase noise
Post by aaron_do on Feb 23^rd, 2014, 9:10pm

Thanks carl,

anyway I found out that the spurs were caused by insufficient supply decoupling. Now I'm trying to figure out how much supply decoupling I need. So I'm running transient analysis with AC times set to a zero crossing value after the PLL is settled. My intention is to find the AC voltage to phase gain from the supply to the output node. That way I can judge the maximum allowable supply ripple. From there I guess I will see what kind of current spikes my design is taking, and based on the bondwire inductance, calculate the supply decoupling cap.

Not sure whether that makes sense, or should I simply iterate a few times until I get good enough performance :P

Aaron

Title: Re: PLL reference spurs, and jitter vs phase noise
Post by carlgrace on Feb 24^th, 2014, 11:47am

Hi Aaron,

Are you using an LDO to supply the VCO in your loop? In practice the low PSRR of the VCO ends up dominating your jitter (it has more of an effect than thermal noise of the VCO).

If your spurs where from supply coupling be very careful about noise coupling!

Title: Re: PLL reference spurs, and jitter vs phase noise
Post by aaron_do on Feb 24^th, 2014, 4:37pm

Hi carl,

yes I'm using an LDO for the VCO. The jitter in the loop is good. The node that I'm probing is outside of the VCO after several stages of buffering, and if fed from the main supply. Thanks anyways for the warning,

Aaron