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https://designers-guide.org/forum/YaBB.pl Simulators >> Circuit Simulators >> ADC verification in cadence https://designers-guide.org/forum/YaBB.pl?num=1395232484 Message started by jesseyu on Mar 19th, 2014, 5:34am |
Title: ADC verification in cadence Post by jesseyu on Mar 19th, 2014, 5:34am Hi, I have an ADC with differential input and it has quite large gain errors across corners, so there is very large inl and constant dnl error. However, What I really want to see is only how ADC's dnl and inl with respect to one specific corner rather than real ADC model. How can I manipulate the script to fulfill the purpose? :-? |
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