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Design >> RF Design >> OPTIMIZATION TECHNIQUES FOR RF CMOS CIRCUITS
https://designers-guide.org/forum/YaBB.pl?num=1396191992

Message started by Mir on Mar 30^th, 2014, 8:06am

Title: OPTIMIZATION TECHNIQUES FOR RF CMOS CIRCUITS
Post by Mir on Mar 30^th, 2014, 8:06am

What should be an approach to achieve a low noise figure in a RF Cmos circuit while doing optimization

Title: Re: OPTIMIZATION TECHNIQUES FOR RF CMOS CIRCUITS
Post by aaron_do on Apr 3^rd, 2014, 2:51am

Your question is way too general. So as a very general answer, I would say keep the design simple and maximize your gain. But really if you just follow that you might end up with the lowest noise circuit in the world that doesn't work properly.

Aaron

Title: Re: OPTIMIZATION TECHNIQUES FOR RF CMOS CIRCUITS
Post by Mir on Apr 3^rd, 2014, 6:08am

thanks Mr. Aaron

Actually i had designed a Wideband Rf Mixer (2-6GHz)...though m getting gain quite high (23dB)but at the same time Noise figure is (37dB SSb)...i.e NF is such a big concern here

Title: Re: OPTIMIZATION TECHNIQUES FOR RF CMOS CIRCUITS
Post by aaron_do on Apr 3^rd, 2014, 6:31pm

That's an unusually high NF even without an LNA. Is your output frequency below the flicker noise corner? Does it match simulations? Maybe there's a problem with your circuit.

regards,
Aaron