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Simulators >> RF Simulators >> Hidden state in resettable D-FlipFlop model "dff2"???
https://designers-guide.org/forum/YaBB.pl?num=1396302674

Message started by spectrallypure on Mar 31^st, 2014, 2:51pm

Title: Hidden state in resettable D-FlipFlop model "dff2"???
Post by spectrallypure on Mar 31^st, 2014, 2:51pm

Hi all! For a PLL design I am using a behavioral model of a phase-and-frequency detector (PFD) built using 2 resettable D-FlipFlops and some ideal logic gates. The problem is that I am unable to run PSS/PNOISE simulations (spectre 12.1.0.457.isr8 64bit) to evaluate the phase noise due a "hidden state" issue:

Code:

Error found by spectre during periodic steady state analysis `pss'.
ERROR (SPCRTRF-15177): PSS analysis doesn't support behavioral module components with hidden states found in component 'dff2'. Skipped.
[...]/dff2__0v1/veriloga/veriloga.va, declared in line 40: Hidden state variable: state
Analysis `pss' was terminated prematurely due to an error.

This seems surprising, since I am using the "dff2" model from http://www.designers-guide.org/verilogams/rf-models/dff/dff.va, which is supposed to be PSS-friendly!

Am I missing something here? Is it really possible to use this model with PSS? If not, could somebody please point me to any Verilog-A model that I could use for my PFD?

Thanks in advance for any help/ideas!

Cheers,

Jorge.

Title: Re: Hidden state in resettable D-FlipFlop model "dff2"???
Post by spectrallypure on Mar 31^st, 2014, 3:03pm

BTW, I am aware of this old post http://www.designers-guide.org/Forum/?board=rfsim;action=display;num=1033687038; unfortunately, it does not deal with a resettable flip-flop model. Are resettability and and hidden-state-freedom mutually-exclusive conditions? :|

Title: Re: Hidden state in resettable D-FlipFlop model "dff2"???
Post by Ken Kundert on Apr 2^nd, 2014, 12:48pm

Do not post the same message to multiple boards.

Quote:

Are resettability and and hidden-state-freedom mutually-exclusive conditions?

No.

I don't know why the model no longer works as intended in Spectre. Conceptually it should.

You might try using the (* instrument_module *) and (* ignore_state *) attributes. I don't remember the exact syntax for these, hopefuly you can find it by reading the manual.

These attributes tell the simulator to stop complaining and just try it. If the simulator fails to converge, well you were warned. If it works, then fortune is smiling on you today and you should consider buying a lottery ticket.

The Instrument Module attribute is intended to mark complex stimulus block (like a complex modulation source) and tells Spectre to ignore any hidden-state issues in the entire module. The Ignore State attribute does the same for only a particular variable. It is good for variables that maintain a value from one time step to the next, but either would not change during an RF analysis (such as a seed variable) or that does not affect the behavior of the block in any significant way (such as warning given flag).

-Ken

Title: Re: Hidden state in resettable D-FlipFlop model "dff2"???
Post by Andrew Beckett on Apr 7^th, 2014, 2:31pm

Ken,

Looking at the two models in that file, dff is OK for hidden-state, but dff2 definitely isn't. The state variable is only updated within an @(cross(...)) block or with an @(initial_step) block. The rest of the time it is retaining state. So perhaps it's the comments at the top which are misleading as I'm guessing they only apply to the first module in the file and not the second?

Regards,

Andrew.

Title: Re: Hidden state in resettable D-FlipFlop model "dff2"???
Post by spectrallypure on Apr 7^th, 2014, 2:57pm

Dear Ken, Andrew;

thanks so much for the replies. In fact, from the comments in the header of the .va file it was not clear to me if the model dff2 is supposed to be also hidden-state free. I tried adding the (* ignore_state *) attribute to the variable "state", but the simulator still complained of a hidden state:

Code:

Error found by spectre during periodic steady state analysis `pss'.
ERROR (SPCRTRF-15177): PSS analysis doesn't support behavioral module components with hidden states found in component 'dff2'. Skipped.
[...]/tb__dff2__mod_0v1/veriloga/veriloga.va, declared in line 44: Hidden state variable: state
Analysis `pss' was terminated prematurely due to an error.

Only defining the (* instrument_module *) attribute on the whole dff2 module makes the PSS run. However, I am still unsure if the results I am getting from my PNOISE simulation using this approach are realiable, I am currently in the process of validating them; I'll let you know what conclusion I arrive to.

BTW, I had no luck finding an alternative implementation of a resettable D Flip-Flop without a hidden state. :\

Thanks again you both for your help.

Cheers,

Jorge.

Title: Re: Hidden state in resettable D-FlipFlop model "dff2"???
Post by spectrallypure on Apr 7^th, 2014, 4:22pm

RESULTS UPDATE: when I try to run a PSS on my PLL behavioral model including a PFD model built using the "dff2" Verilog-A flip-flops, Spectre gives me the following warnings:

Code:

Warning from spectre during IC analysis, during periodic steady state analysis `pss'.
WARNING (ASL-4801): "[...]/dff2__mod_0v1/veriloga/veriloga.va" 61: PFD.DFF2: idt( expression ), where expression is a constant or parameter expression, generates a nonperiodic system variable, prohibiting PSS convergence. Consider using idtmod( expression ) instead.
WARNING (ASL-4801): "[...]/dff2__mod_0v1/veriloga/veriloga.va" 61: PFD.DFF1: idt( expression ), where expression is a constant or parameter expression, generates a nonperiodic system variable, prohibiting PSS convergence. Consider using idtmod( expression ) instead.
Notice from spectre during IC analysis, during periodic steady state analysis `pss'.

and then the PSS does not converge. The tstab portion of the simulation seems to be OK (using the "saveinit" option I am able to see the evolution of the VCO control voltage, and it agrees with the behavior I observe in transient simulations for a successful locking of the PLL). The problem seems to appear afterwards, during the "shooting window" portion of the PSS; please find below an abridged version of my simulation log.

I am not sure if the PSS convergence problem is related to the presence of the "dff2" flops or if it is a problem somewhere else with my other models or with my PSS settings. I would be really grateful if you could please point out what could be the problem (should I maybe start a dedicated post for this issue?)

Thanks in advance for any help.

Cheers,

Jorge.

Title: Re: Hidden state in resettable D-FlipFlop model "dff2"???
Post by spectrallypure on Apr 7^th, 2014, 4:25pm

Code:

Simulating `input.scs' on ix1186 at 6:38:50 PM, Mon Apr 7, 2014 (process id: 10680).
Current working directory: /local/[...]/Sim/PLL__testbench__1v0/spectre/schematic/netlist.
Environment variable:
SPECTRE_DEFAULTS=-I.
Command line:
\
/sw/cds/MMSIM/MMSIM_12_1_Linux/tools.lnx86/spectre/bin/64bit/spectre \
input.scs +escchars +log ../psf/spectre.out -format psfxl -raw \
../psf ++aps +cktpreset=pll +lqtimeout 900 -maxw 5 -maxn 5 \
+lsuspend

Notice from spectre during topology check.
Only one connection to the following 2 nodes:
PD_LATEn
PFD.net010
No DC path from node `CP__out' to ground, Gmin installed to provide path.

***************************************************
Periodic Steady-State Analysis `pss': fund = 20 kHz
***************************************************

Warning from spectre during IC analysis, during periodic steady state analysis `pss'.
WARNING (ASL-4801): "[...]/dff2__mod_0v1/veriloga/veriloga.va" 61: PFD.DFF2: idt( expression ), where expression is a constant or parameter expression, generates a nonperiodic system variable, prohibiting PSS convergence. Consider using idtmod( expression ) instead.
WARNING (ASL-4801): "[...]/dff2__mod_0v1/veriloga/veriloga.va" 61: PFD.DFF1: idt( expression ), where expression is a constant or parameter expression, generates a nonperiodic system variable, prohibiting PSS convergence. Consider using idtmod( expression ) instead.
Notice from spectre during IC analysis, during periodic steady state analysis `pss'.
GminDC = 1 aS is large enough to noticeably affect the DC solution.
dV(vCTRL) = -13.2684 uV
Use the `gmin_check' option to eliminate or expand this report.

DC simulation time: CPU = 9.998 ms, elapsed = 13.0072 ms.

Notice from spectre during periodic steady state analysis `pss'.
Multithreading is disabled due to the size of the design being too small.

================================
`pss': time = (0 s -> 100.07 ms)
================================
Important parameter values in tstab integration:
start = 0 s
outputstart = 0 s
stop = 100.07 ms
period = 50 us
step = 100.07 us
maxstep = 2 us
ic = all
useprevic = no
skipdc = no
reltol = 1e-09
abstol(V) = 1 uV
abstol(I) = 1 fA
temp = 27 C
tnom = 27 C
tempeffects = all
method = traponly
lteratio = 0
relref = sigglobal
cmin = 0 F
gmin = 1 aS
rabsshort = 1 mOhm

pss: time = 72.61 us (72.6 m%), step = 5.054 ns (5.05 u%)
pss: time = 126.3 us (126 m%), step = 6.916 ps (6.91 n%)
[...]
pss: time = 18.03 ms (18 %), step = 631.6 ps (631 n%)
pss: time = 18.08 ms (18.1 %), step = 3.176 ps (3.18 n%)
pss: time = 18.13 ms (18.1 %), step = 25.54 ns (25.5 u%)
Warning from spectre at time = 18.1734 ms during periodic steady state analysis `pss'.
WARNING (SPECTRE-16191): Minimum time step used. Solution might be in error.
pss: time = 18.18 ms (18.2 %), step = 17.74 ps (17.7 n%)
pss: time = 18.23 ms (18.2 %), step = 9.912 ns (9.91 u%)
pss: time = 18.29 ms (18.3 %), step = 1.628 ns (1.63 u%)
pss: time = 18.34 ms (18.3 %), step = 161.9 ps (162 n%)
pss: time = 18.39 ms (18.4 %), step = 13.94 ns (13.9 u%)
Warning from spectre at time = 18.4234 ms during periodic steady state analysis `pss'.
WARNING (SPECTRE-16191): Minimum time step used. Solution might be in error.
pss: time = 18.44 ms (18.4 %), step = 1.758 ns (1.76 u%)
Warning from spectre at time = 18.4734 ms during periodic steady state analysis `pss'.
WARNING (SPECTRE-16191): Minimum time step used. Solution might be in error.
pss: time = 18.5 ms (18.5 %), step = 20.41 ps (20.4 n%)
Warning from spectre at time = 18.5234 ms during periodic steady state analysis `pss'.
WARNING (SPECTRE-16191): Minimum time step used. Solution might be in error.
Further occurrences of this warning will be suppressed.
pss: time = 18.55 ms (18.5 %), step = 255.2 ps (255 n%)
pss: time = 18.6 ms (18.6 %), step = 285.1 ps (285 n%)
[...]
pss: time = 99.87 ms (99.8 %), step = 399.8 ps (400 n%)
pss: time = 99.92 ms (99.9 %), step = 413.6 ps (414 n%)
pss: time = 99.97 ms (100 %), step = 1.556 ps (1.56 n%)

Title: Re: Hidden state in resettable D-FlipFlop model "dff2"???
Post by spectrallypure on Apr 7^th, 2014, 4:26pm

Code:

======================================
`pss': time = (100.02 ms -> 100.07 ms)
======================================
pss: time = 100 ms (2.54 %), step = 25.06 ns (50.1 m%)
pss: time = 100 ms (7.52 %), step = 10.02 ns (20 m%)
[...]
pss: time = 100 ms (57.5 %), step = 9.609 ns (19.2 m%)
pss: time = 100.1 ms (62.5 %), step = 2.88 ns (5.76 m%)
pss: time = 100.1 ms (67.5 %), step = 16.92 ns (33.8 m%)
pss: time = 100.1 ms (72.5 %), step = 182.9 ps (366 u%)
pss: time = 100.1 ms (77.5 %), step = 25.12 ns (50.2 m%)
pss: time = 100.1 ms (82.5 %), step = 9.61 ns (19.2 m%)
pss: time = 100.1 ms (87.5 %), step = 2.896 ns (5.79 m%)
pss: time = 100.1 ms (92.5 %), step = 16.84 ns (33.7 m%)
pss: time = 100.1 ms (97.5 %), step = 187.1 ps (374 u%)
Conv norm = 2.2e+06, max dV(CLK_FB) = 2.2 V, took 18.8949 ks.

Important parameter values in pss iteration:
start = 100.02 ms
outputstart = 0 s
stop = 100.07 ms
period = 50 us
steadyratio = 10e-03
step = 100.07 us
maxstep = 250 ns
ic = all
useprevic = no
skipdc = no
reltol = 1e-09
abstol(V) = 1 uV
abstol(I) = 1 fA
temp = 27 C
tnom = 27 C
tempeffects = all
errpreset = conservative
method = gear2only
lteratio = 0
relref = alllocal
cmin = 0 F
gmin = 1 aS
rabsshort = 1 mOhm

Notice from spectre during periodic steady state analysis `pss'.
623 warnings suppressed.

======================================
`pss': time = (100.02 ms -> 100.07 ms)
======================================
pss: time = 100 ms (2.53 %), step = 20.09 ns (40.2 m%)

Warning from spectre at time = 100.023 ms during periodic steady state analysis `pss'.
WARNING (SPECTRE-16191): Minimum time step used. Solution might be in error.

pss: time = 100 ms (7.5 %), step = 7.836 ns (15.7 m%)
pss: time = 100 ms (12.5 %), step = 2.244 ns (4.49 m%)
[...]
pss: time = 100 ms (57.5 %), step = 8.138 ns (16.3 m%)
pss: time = 100.1 ms (62.5 %), step = 2.154 ns (4.31 m%)
pss: time = 100.1 ms (67.5 %), step = 13.44 ns (26.9 m%)
pss: time = 100.1 ms (72.5 %), step = 118.1 ps (236 u%)
pss: time = 100.1 ms (77.5 %), step = 19.87 ns (39.7 m%)
pss: time = 100.1 ms (82.5 %), step = 8.139 ns (16.3 m%)
pss: time = 100.1 ms (87.5 %), step = 2.193 ns (4.39 m%)
pss: time = 100.1 ms (92.5 %), step = 13.44 ns (26.9 m%)
pss: time = 100.1 ms (97.5 %), step = 93.63 ps (187 u%)
Conv norm = 1.94e+03, max dV(VCO.vOUTm) = -1.93605 mV, took 16.12 s.

Title: Re: Hidden state in resettable D-FlipFlop model "dff2"???
Post by spectrallypure on Apr 7^th, 2014, 4:27pm

Code:

======================================
`pss': time = (100.02 ms -> 100.07 ms)
======================================

Error found by spectre at time = 100.18 ms during periodic steady state analysis `pss'.
ERROR (SPECTRE-16192): No convergence achieved with the minimum time step specified.
Warning from spectre at time = 100.18 ms during periodic steady state analysis `pss'.
WARNING (SPECTRE-223): Detected NaN at node vdda.
WARNING (SPECTRE-223): Detected NaN at node VCO.vCm.
WARNING (SPECTRE-223): Detected NaN at node VCO.vCp.
WARNING (SPECTRE-223): Detected NaN at node VCO.vOUTp.
WARNING (SPECTRE-223): Detected NaN at node VCO.vOUTm.
Further occurrences of this warning will be suppressed.

The values for those nodes that did not converge on the last Newton iteration are given below. The manner in which the convergence criteria were not satisfied is also given.
Failed test: | Value | > RelTol*Ref + AbsTol

Top 10 Residue too large Convergence failure:
V(IREF) = -918.999 V, previously -918.998 V.
residue too large: | 1.64602 GA | > 1.64602 A + 1 fA
V(VCO.net0100) = 548.531 V, previously 548.53 V.
residue too large: | -160.4 MA | > 160.4 mA + 1 fA
V(CLK_OUT) = -138.369 V, previously -138.369 V.
residue too large: | 7.90526 MA | > 7.90526 mA + 1 fA
V(VCO.VBP) = 116.757 kV, previously 116.757 kV.
residue too large: | -48.5193 GA | > 48.5193 A + 1 fA
V(VCO.VBN) = 1.05343 MV, previously 1.05343 MV.
residue too large: | -383.318 GA | > 383.318 A + 1 fA
V(VCO.net099) = -727.094 kV, previously -727.094 kV.
residue too large: | 368.379 GA | > 368.379 A + 1 fA
V(VCO.vOUT_SE) = -326.851 kV, previously -326.851 kV.
residue too large: | 32.1582 GA | > 32.1582 A + 1 fA
V(VCO.net066) = -706.18 kV, previously -706.18 kV.
residue too large: | 98.7565 GA | > 98.7565 A + 1 fA
V(VCO.vD2SEp) = 15.1154 MV, previously 15.1154 MV.
residue too large: | -2.76751 TA | > 2.76751 kA + 1 fA
V(VCO.net0101) = -80.8812 kV, previously -80.8812 kV.
residue too large: | 280.502 A | > 280.502 nA + 1 fA

The following set of suggestions might help you avoid convergence difficulties.

1. Evaluate and resolve any notice, warning, or error messages.
2. Use realistic device models. Check all component parameters, particularly nonlinear device model parameters, to ensure that they are reasonable.
3. Small floating resistors connected to high impedance nodes can cause convergence difficulties. Avoid very small floating resistors, particularly small parasitic resistors in semiconductors. Instead, use voltage sources or iprobes to measure current.
4. Ensure that a complete set of parasitic capacitors is used on nonlinear devices to avoid jumps in the solution waveforms. On MOS models, specify nonzero source and drain areas.
5. Perform sanity check on the parameter values by using the parameter range checker (use ``+param param-limits-file'' as a command line argument) and heed any warnings. Print the minimum and maximum parameter value by using `info' analysis. Ensure that the bounds given for instance, model, output, temperature-dependent, and operating-point (if possible) parameters are reasonable.

6. Check the direction of both independent and dependent current sources. Convergence problems might result if current sources are connected such that they force current backward through diodes.

7. Enable diagnostic messages by setting option `diagnose=yes'.
8. Use the `cmin' parameter to install a small capacitor from every node in the circuit to ground. This usually eliminates any jump in the solution.
9. Loosen tolerances, particularly absolute tolerances like `iabstol' (on options statement). If tolerances are set too tight, they might preclude convergence.
10. Try to simplify the nonlinear component models to avoid regions that might contribute to convergence problems in the model.

Conv norm = 2.2e+06, max dV(CLK_IN) = -2.2 V, took 0 s.

Analysis `pss' was terminated prematurely due to an error.

Notice from spectre.
4 warnings suppressed.

modelParameter: writing model parameter values to rawfile.
element: writing instance parameter values to rawfile.

Warning from spectre during info `element'.
WARNING (SPECTRE-16518): Arithmetic exception in analysis `element' .

Aggregate audit (11:54:35 PM, Mon Apr 7, 2014):
Time used: CPU = 18.9 ks (5h 15m 12s), elapsed = 18.9 ks (5h 15m 45s), util. = 99.8%.
Time spent in licensing: elapsed = 731 ms.
Peak memory used = 185 Mbytes.
Simulation started at: 6:38:50 PM, Mon Apr 7, 2014, ended at: 11:54:35 PM, Mon Apr 7, 2014, with elapsed time (wall clock): 18.9 ks (5h 15m 45s).
spectre completes with 1 error, 26 warnings, and 10 notices.

Title: Re: Hidden state in resettable D-FlipFlop model "dff2"???
Post by Ken Kundert on Apr 8^th, 2014, 12:35am

Andrew,
I think dff2 is okay. The variable state is ignored by the idt operator except when ActNow is nonzero, and that is only true on the time point where state is updated. So, while state may represent hidden state, from the perspective of the model it appears stateless.

-Ken

Title: Re: Hidden state in resettable D-FlipFlop model "dff2"???
Post by Ken Kundert on Apr 8^th, 2014, 12:38am

spectrallypure,
If PSS is not converging while simulating the entire PLL, there may be any number of problems. Did you at least use strobing to assure that there is a periodic solution and that tstab is set long enough to approach it.

-Ken

Title: Re: Hidden state in resettable D-FlipFlop model "dff2"???
Post by Andrew Beckett on Apr 8^th, 2014, 2:00am

Ken Kundert wrote on Apr 8^th, 2014, 12:35am:

Ken,

Good point. I guess it's a bit hard for spectre to infer that though.

spectrallypure - if you use the ignore_state attribute in current versions of the simulator, it says:

WARNING (VACOMP-2351): "(* ignore_state *)<<--? integer actNow, out, state;"
"dff.va", line 48: Encountered the 'ignore_state' attribute, which is obsolete and no longer supported. To
ignore the state of a Verilog-A module, use the 'ignore_hidden_state' module attribute instead.

So rather than putting the ignore_state attribute on individual variables, instead using:

(* ignore_hidden_state *) module dff2 (clk, d, reset, q, qb);

did the job. This converges fine for me in my simple testbench - as Ken said, the convergence issue is probably related to the rest of the PLL.

Regards,

Andrew.

Title: Re: Hidden state in resettable D-FlipFlop model "dff2"???
Post by Ken Kundert on Apr 8^th, 2014, 10:54am

Quote:

GminDC = 1 aS

Really? Because 1TΩ is a million times too small?