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https://designers-guide.org/forum/YaBB.pl Design Languages >> Verilog-AMS >> differential clock d flip flop verilog-a model https://designers-guide.org/forum/YaBB.pl?num=1399618623 Message started by mahesh venkatt on May 8th, 2014, 11:57pm |
Title: differential clock d flip flop verilog-a model Post by mahesh venkatt on May 8th, 2014, 11:57pm Dear All, this is the sample code i am using for simulating analog d-ff with single vclk input. ==================================================== integer x; analog begin @ (cross( V(vclk) - vtrans_clk, +1 )) begin x = (V(vin_d) > vtrans); end V(vout_q) <+ transition( vlogic_high*x + vlogic_low*!x, tdel, trise, tfall ); V(vout_qbar) <+ transition( vlogic_high*!x + vlogic_low*x, tdel, trise, tfall ); end ==================================================== can somebody give me some idea how to model differential clock (vclk, vclk_bar) d-flip flop? Thanks Mahesh |
Title: Re: differential clock d flip flop verilog-a model Post by boe on May 9th, 2014, 7:20am mahesh venkatt, you should check the crossing of vclk & vclk_bar to sample the input. - B O E |
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