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Simulators >> Circuit Simulators >> Cadence transient PLL simulation results vary with different accuracy settings
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Message started by Faye on May 14^th, 2014, 12:30pm

Title: Cadence transient PLL simulation results vary with different accuracy settings
Post by Faye on May 14^th, 2014, 12:30pm

I am simulating a circuit level PLL. I obtained the component parameters from system level simulation and everything should work. I came across this problem that if I run the transient simulation and set the accuracy (errpreset) to be

1) errpreset=liberal ==> system locks and the result is good
2) errpreset=moderate ==> system locks and the result is good
3) errpreset=conservative ==> unreasonable result and system won't lock

Sometimes if I run case 3) for a long time, the result is getting correct again. For example, if I run for 0.5us with conservative accuracy, the system won't lock (with moderate or liberal, it will lock at around 0.2us). However, if I run for 3us with conservative accuracy, the result is totally different: it locks at 0.2us and behaves exactly the same with the rest two (moderate or liberal).

Has anyone experienced the same problem before? Any suggestions will be highly appreciated.

Faye

Title: Re: Cadence transient PLL simulation results vary with different accuracy settings
Post by Ken Kundert on May 14^th, 2014, 5:58pm

You have provided very little information to go on, so there is little help than we can give. But I would remind you that the PLL lock process can be chaotic. Very small changes can result in very different results. Is it possible that all of the results are correct?

-Ken

Oh, and do not ask simulations questions in the design boards.

Title: Re: Cadence transient PLL simulation results vary with different accuracy settings
Post by sheldon on May 19^th, 2014, 12:37am

Faye,

If you have access to the calculator, then you might want to plot
the VCO output frequency to check the settling of the loop. The
other option is to plot the reference frequency, a constant, and
divider frequency to see how the PLL loop is settling. The other
net to look at is the LPF node, is it within the expected range or
not? If the output of the Charge Pump is out of range then the
VCO maybe running free.

Best Regards,

Sheldon

Title: Re: Cadence transient PLL simulation results vary with different accuracy settings
Post by Faye on May 19^th, 2014, 3:03pm

Ken Kundert wrote on May 14^th, 2014, 5:58pm:

Ken,

Sorry for posting questions on the wrong board.. actually it was my first post here :)

My problem is from transient simulation, with moderate accuracy, the PLL locks but with conservative accuracy, the PLL won't lock (see the attached figures showing the transient control voltage). If all the results are correct, my concern is what if in the real world, will the PLL work or not? I am just not sure if it is because my design is bad or something else.

I was also told that a tight accuracy may result in the converging problems and give flaky results. Will that be possible?

Many thanks for your advices!

Best,
Faye

Title: Re: Cadence transient PLL simulation results vary with different accuracy settings
Post by Faye on May 19^th, 2014, 3:08pm

sheldon wrote on May 19^th, 2014, 12:37am:

Sheldon,

I did plot the control voltage vs. time (see the above post). I also plotted the output frequency. The problem is if I run transient simulation and set the accuracy to be moderate, the Vctrl will settle down in an appropriate time and the output frequency will lock to the reference signal. However, if I set the accuracy to be conservative, the Vctrl will just fluctuate and the output wont lock.

Any advices will be highly appreciated.

Best,
Faye

Title: Re: Cadence transient PLL simulation results vary with different accuracy settings
Post by sheldon on May 20^th, 2014, 6:53am

Faye,

It is difficult to understand how your PLL is designed to perform,
however, here are some observations:
1) It appears that you need to run the simulation longer for the
conservative error preset. The simulation does not appear to
be misbehaving, just that you haven't allowed it to fully settle
2) The PLL PFD appears to have a dead zone. For the moderate error
preset, the loop appears to be open, in the dead zone of the
PFD.

Sheldon