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Design >> RF Design >> RF switch gate-oxide breakdown
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Message started by rf_man on May 22^nd, 2014, 1:00pm

Title: RF switch gate-oxide breakdown
Post by rf_man on May 22^nd, 2014, 1:00pm

Hi,

I have a question about the gate-oxide breakdown of RF CMOS switch. Usually the gate and substrate are bootstraped with large resistances (in the order of tens of kilo ohms), and the drain/source usually bias at higher voltage instead of at 0V. For example, in a process with nominal breakdown voltage equals to 2.5V, the drain/source is biased at 2.5V, and the gate swithing voltage is 5/0V. When the gate is biased at 5V, the gate-bulk voltage is 5V, which exceeds the gate-oxide voltage of 2.5V. I don't undertand why this is not a problem here, seems to be related to the bootstrap at both gate and bulk. Can anyone explain this?

Kind regards,

Junior RF man

Title: Re: RF switch gate-oxide breakdown
Post by loose-electron on May 22^nd, 2014, 3:59pm

take a close look at how your foundry defines the voltage between:

1. gate
2. bulk under the gate

and how they put the the limitations placed on it.

The details of this vary between foundries and how they do the test and define the limits.

Title: Re: RF switch gate-oxide breakdown
Post by aaron_do on May 22^nd, 2014, 8:24pm

Hi,

I asked a similar question a while ago. The answer given was because when the transistor is ON, the channel is at 2.5 V, not 0 V. So there is no breakdown issue...seems correct to me.

regards,
Aaron

Title: Re: RF switch gate-oxide breakdown
Post by rf_man on May 23^rd, 2014, 7:18am

Thanks Aaron. Indeed that sounds making sense.

Kind regards,

rf_man