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Simulators >> RF Simulators >> Is the simulated phase noise related to "the estimated line width of the oscill"
https://designers-guide.org/forum/YaBB.pl?num=1401270914

Message started by Kyle on May 28^th, 2014, 2:55am

Title: Is the simulated phase noise related to "the estimated line width of the oscill"
Post by Kyle on May 28^th, 2014, 2:55am

Hi, everyone,
I have simulated a TITO VCO in Cadence by PSS and Pnoise (Ref. 08_JSSC_CMOS VCO and LNA Using Tuned-Input Tuned-Output Circuits). But, I found that the Phase noise is variable and it seemed that the value of phase noise can be smaller with small "estimated line width"

Is there anybody knows whether there exits a relationship between the phase noise and the estimated line width?

Title: Re: Is the simulated phase noise related to "the estimated line width of the oscill"
Post by Ken Kundert on May 28^th, 2014, 3:19pm

See equation 25 in http://www.designers-guide.org/Analysis/PLLnoise+jitter.pdf

-Ken