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Design >> Analog Design >> 8-bit 50MS/s ADC architecture choice
https://designers-guide.org/forum/YaBB.pl?num=1402766907

Message started by neoflash on Jun 14^th, 2014, 10:28am

Title: 8-bit 50MS/s ADC architecture choice
Post by neoflash on Jun 14^th, 2014, 10:28am

Hi,

The requirement is to have 50MS/s data throughput. I have two choices:

1. pipelined ADC
2. 8-way interleaved SAR

The technology will be on 0.18um. Which topology will be more efficient in power/area?

Regards,
Neo

Title: Re: 8-bit 50MS/s ADC architecture choice
Post by loose-electron on Jun 14^th, 2014, 6:15pm

probably a pipe will get it done in less space - interleaving a pile of converters brings up a bunch of problems beyond just power and area.

plenty of papers on the topic out there, time to start doing some research

Title: Re: 8-bit 50MS/s ADC architecture choice
Post by neoflash on Jun 14^th, 2014, 8:48pm

loose-electron wrote on Jun 14^th, 2014, 6:15pm:

Thank you for your reply. The application seems to sample DC signal and greatly relieves timing mismatch issue.

Given this case, is SAR more attractive?

Title: Re: 8-bit 50MS/s ADC architecture choice
Post by loose-electron on Jun 20^th, 2014, 7:48pm

8 interleaved SAR devices is a big headache in alignment and matching

Title: Re: 8-bit 50MS/s ADC architecture choice
Post by ywguo on Jun 20^th, 2014, 10:40pm

Hi Neo,

Why do you design a 50MS/s ADC to sample DC signal? What's your application?

Best Regards,
Yawei