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Design Languages >> Verilog-AMS >> Changing clk period dynamically
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Message started by satvika on Jun 26^th, 2014, 3:28am

Title: Changing clk period dynamically
Post by satvika on Jun 26^th, 2014, 3:28am

Hi,

I am generating triangular wave using the following code. I am instantiating this in top level module. Is there a way I can change the value of period on the fly, if I need to change from one frequency to another.

module V_triangle_generator(out);
output out;
voltage out;

parameter real period = 10n from [0:inf),
ampl = 1;

integer slope;
real offset;

analog
begin
@(timer(0,period))
begin
slope = +1;
offset = $realtime;
discontinuity(1);
end

@(timer(period/2,period))
begin
slope = -1;
offset = $realtime;
discontinuity(1);
end

V(out) <+ ampl * slope * (4*($realtime-offset)/period - 1);
end
endmodule

Thanks in advance

Title: Re: Changing clk period dynamically
Post by boe on Jun 26^th, 2014, 9:17am

Satvika,
my V-AMS documentation states "[p]arameters are constants, so you cannot change the value of a parameter at runtime", so you need to change the definition of the period to a variable.
You will probably need to change the timer() implementation to make sure that no phase jumps can occur.
- B O E