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Design >> Analog Design >> Relaxing the matching requirement in first stage of Pipeline ADC
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Message started by SNIKE on Jul 22^nd, 2014, 12:35am

Title: Relaxing the matching requirement in first stage of Pipeline ADC
Post by SNIKE on Jul 22^nd, 2014, 12:35am

Hi Members,

I have a question in pipeline ADC's.
I am designing the following bits per stage

4bits per stage first stage followed by 9 1.5 bits/stage.
There is a digital correction so end number of bits is 12Bits.

Since the first sub ADC already resolved the MSB's, does this mean that my first MDAC/gain stage capacitor matching requirement is only 9Bit and not 12 bit?? Since only the residue plot is sent to subsequent stages?

Please enlighten me on this?

Thanks in advance.

Title: Re: Relaxing the matching requirement in first stage of Pipeline ADC
Post by aaron_do on Jul 22^nd, 2014, 1:22am

Hi,

if you split up the operation, you can think of it as first calculate the residue and then amplify. In that case, the residue needs to be 12b accurate wrt the full scale input of the ADC, but only 9b accurate wrt the maximum swing of the residue. After amplification, it needs to be 9b accurate wrt full scale. But anyway I guess you can't look at an actual MDAC so simply. Of course, the output after amplification needs to be 9b accurate wrt full scale.

regards,
Aaron

Title: Re: Relaxing the matching requirement in first stage of Pipeline ADC
Post by SNIKE on Jul 22^nd, 2014, 1:31am

Yes I was thinking on the same lines.
The "Residue" needs to be 12 bit, which doesn't depend on capacitor matching. The residue is a sample of vin and DAC out, and at this point the ratio of capacitors still don't come in to picture.
The gain depends on capacitor matching, which requires to be only 9bit.

Let me know if my thinking process is wrong.

Title: Re: Relaxing the matching requirement in first stage of Pipeline ADC
Post by carlgrace on Jul 22^nd, 2014, 5:41pm

I'm confused by the terminology you and Aaron are using. Typically "residue" refers to the analog MDAC output, so the cap matching is part of it. If you think of the residue of a stage as an analog representation of the quantization error of the stage's sub-ADC it should be obvious that converting more bits in a stage relaxes the requirements on the MDAC of that stage.

So, if you have a 4-bit first stage (i'm guessing it's really 3.5-bit??) then, yes, your MDAC only needs to settle to 1/2 LSB @ 9 bits.

Title: Re: Relaxing the matching requirement in first stage of Pipeline ADC
Post by SNIKE on Jul 22^nd, 2014, 6:04pm

thanks carl,

by "residue" I meant Vin-Vin_digital.
I should have clarified it.

Thanks
Sai

Title: Re: Relaxing the matching requirement in first stage of Pipeline ADC
Post by carlgrace on Jul 22^nd, 2014, 10:28pm

hmmmm.... vin - vin_digital is not actually a term that exists in the ADC. Did you mean vin minus the analog form of the reconstructed vin_digital? This is what is typically called a residue.

Recall that in practical pipelined ADCs the sampling, gain, and subtraction are done by a single circuit (the MDAC) so the idea of vin - vin_digital doesn't have physical meaning.

If you're designing the ADC in a standard way the residue accuracy requirement of the first stage would be 9 bits.

Title: Re: Relaxing the matching requirement in first stage of Pipeline ADC
Post by SNIKE on Jul 22^nd, 2014, 11:33pm

Yes I meant Vin-VdacOutput.
In my head I am trying to imagine in following way:
Step 1) Vin is sampled on a capacitor.
Step 2) Vin is partially digitized by sub ADC, this code is converted in to Analog form [ for example + vref , 0 or -vref].
step 3) subtract Vin - Vdacoutput.
Step 4) send them trough a gain stage. This gain stage depends on capacitor ratios, so matching matters here.

even tough some steps occur simultaneously , the above steps help me understand the concept.

Now with your help and Aaron's I understand it fully.
Thanks

Title: Re: Relaxing the matching requirement in first stage of Pipeline ADC
Post by carlgrace on Jul 23^rd, 2014, 10:25am

You're almost there!

Main change I would make to your list is that the step four happens at the same time as steps 2 and 3, so the capacitor ratios matter for all three steps. The reason we use redundancy (such as the 1.5-bit stage) is so that capacitor mismatch in steps 2 and 3 don't affect the overall performance of the converter.

Title: Re: Relaxing the matching requirement in first stage of Pipeline ADC
Post by aaron_do on Jul 23^rd, 2014, 6:29pm

Hi Guys,

first off, carlgrace would know this far better than me.... :P

Anyway I did mention that in a real MDAC you can't look at the operation so simplistically mainly because as carlgrace said the operations happen at once.

I have one question though.

Quote:

The reason we use redundancy (such as the 1.5-bit stage) is so that capacitor mismatch in steps 2 and 3 don't affect the overall performance of the converter.

the residue of the MDAC is digitized by the rest of the ADC which can be modeled as a lower resolution ADC. If the residue is non-linear, then how can redundancy help to correct it? I thought that redundancy corrects for sub-ADC errors.

thanks,
Aaron

Title: Re: Relaxing the matching requirement in first stage of Pipeline ADC
Post by carlgrace on Jul 24^th, 2014, 6:05am

Hi Aaron,

I should have been a bit clearer. The 1.5-bit stage means that cap mismatch doesn't cause nonlinearity in the subDAC (because any two points are linear, or three in a differential sense). So, the only place cap mismatch hurts you is in the gain function of the MDAC when you're using a 1.5-bit stage.

If you're using a multi-bit stage, then you're right, mismatch in the DAC can cause issues. Thanks for pointing that out.

Title: Re: Relaxing the matching requirement in first stage of Pipeline ADC
Post by RobG on Jul 29^th, 2014, 3:42pm

A major part of his question hasn't been answered. Unless you want to calibrate, the first stage capacitor matching does need to be 12 bits. The opamp open loop gain also has to be greater that 2^12 (72 dB). This will ensure that the output of the first MDAC is at least 9 bit accurate.

Also - a minor point, redundancy is used so that the comparators in his 3.5 bit sub-ADC don't have to be 12 bit accurate. Cap mismatch (and low opamp gain) will only cause an error in the gain of the MDAC as Carl pointed out, but that gain error will limit the performance unless it is calibrated out.

Title: Re: Relaxing the matching requirement in first stage of Pipeline ADC
Post by aaron_do on Jul 29^th, 2014, 7:45pm

there needs to be a "like" button or something like that so we can see how many people agree with the comment.

Anyway for the opamp, the gain needs to be even higher to take into account the closed-loop gain right?

Aaron

Title: Re: Relaxing the matching requirement in first stage of Pipeline ADC
Post by RobG on Jul 29^th, 2014, 8:15pm

aaron_do wrote on Jul 29^th, 2014, 7:45pm:

Anyway for the opamp, the gain needs to be even higher to take into account the closed-loop gain right?

A bit higher so that isn't the limiting factor, but the loop gain doesn't figure into it (to first order). For example, suppose you had a 72dB open loop gain opamp. This is (barely) good enough for a 12 bit ADC. (Actually I guess it might need to be 78dB to get within 1/2 LSB.) If you wanted to get 1.5 bits in the first stage your gain would be two and your loop gain would be 66dB. This isn't a problem because the output only has to be good to 11 bits. Similarly, if you were doing 3.5 bits in the first stage you'd want a gain of 8, resulting in a loop gain of 54dB. Again, this is ok since the output only has to be accurate to 9 bits. Does that make sense?

In the real world you'd want more margin... I take as much as is easily achievable so I don't have to worry about it over corners. Or whether it is 72dB or 78dB :). Also, the input capacitance of the opamp reduces the loop gain.

Title: Re: Relaxing the matching requirement in first stage of Pipeline ADC
Post by SNIKE on Jul 29^th, 2014, 8:22pm

"What if we needed much higher resolution than 10 bits?
– Digital calibration
– Multi-bit first stage
• Each extra bit resolved in the first stage alleviates precision
requirements on residue transition by 2x
• For fixed capacitor matching, can show that each (effective) bit
moved into the first stage
– Improves DNL by 2x
– Improves INL by sqrt(2)x
• Multi-bit examples: [Singer 1996] [Kelly 2001] [Lee 2007]
B."

This is from Stanford 315B course by Boris Murmann.
I am confused, this is opposite to the comments in the thread.

Title: Re: Relaxing the matching requirement in first stage of Pipeline ADC
Post by RobG on Jul 29^th, 2014, 9:21pm

Snike - Murmann's observations seem consistent with everything said here.

Title: Re: Relaxing the matching requirement in first stage of Pipeline ADC
Post by SNIKE on Jul 29^th, 2014, 9:39pm

Sorry still confused.
So can I use a capacitors whose matching is just 9 Bit to generate a 12 bit output,assuming my first stage is 4Bit (3.5bit).

Title: Re: Relaxing the matching requirement in first stage of Pipeline ADC
Post by aaron_do on Jul 29^th, 2014, 10:22pm

Hi SNIKE,

I think your best bet is to look at the transfer function and also do some system level simulations. Boris Murmann is probably right...

Aaron

Title: Re: Relaxing the matching requirement in first stage of Pipeline ADC
Post by RobG on Jul 30^th, 2014, 8:47am

SNIKE wrote on Jul 29^th, 2014, 9:39pm:

Sorry still confused.
So can I use a capacitors whose matching is just 9 Bit to generate a 12 bit output,assuming my first stage is 4Bit (3.5bit).

I'm 99% sure you need a 12 bit accurate DAC on the first stage because the errors are multiplied by the increased first stage gain, but after looking at the Kelly paper [Journal of Solid State circuits, Dec 2001] I wonder if I'm wrong.

If anyone can knows why this is true (or false) I'd like to know. I can agree with the paper that the DNL improves by sqrt(2) (contrary to the Murmann claim of 2x) but the number of elements doubles so I think the INL stays the same.

Murmann might be keeping the unit capacitor the same size and doubling the total capacitance, which would give 2x improvement in DNL and sqrt(2) improvement in INL.

Like Aaron says, do some modeling. You can download SciLab for free if you can't use Matlab. Definitely don't blindly believe any paper's equations without understanding the assumptions.

Please let us know the results.

Title: Re: Relaxing the matching requirement in first stage of Pipeline ADC
Post by SNIKE on Jul 30^th, 2014, 10:44am

Hi Rob,

Thanks for pointing me to Kelly's "JSSC".
I was always checking their ISSCC , where they don't talk much about matching.
I am trying to model the ADC, the problem is the model spits out what equations I plug in.
So hand calculation is as good as modelling.

Now I am clear about the matching part. I am convinced that dnl improves by sqrt(2).

Thanks all for the discussions.

Title: Re: Relaxing the matching requirement in first stage of Pipeline ADC
Post by RobG on Jul 30^th, 2014, 11:07am

OK - for what it is worth, meeting your kT/C noise requirement probably requires a big enough capacitor that matching isn't an issue for SNDR.

Title: Re: Relaxing the matching requirement in first stage of Pipeline ADC
Post by carlgrace on Aug 1^st, 2014, 11:03am

RobG wrote on Jul 30^th, 2014, 8:47am:

SNIKE wrote on Jul 29^th, 2014, 9:39pm:

Sorry still confused.
So can I use a capacitors whose matching is just 9 Bit to generate a 12 bit output,assuming my first stage is 4Bit (3.5bit).

The DAC linearity requirement is reduced in a pipelined ADC using a multi-bit first stage because the coarse conversion of the first stage happens BEFORE the residue is generated, it's as simple as that.

If you have a 12-bit converter, and a 3.5-bit first stage, you're converting the 3 MSBs of the your input signal before it even touches the op amp. The output residue will then be converted by the backend of the ADC, which in this case is a 9-bit converter.

This effect is one of the main reasons you use a multi-bit first stage (the other is power dissipation). The idea is if you use a multi-bit first stage you can make a 12-bit linear ADC with 10-bit capacitor matching (for instance).

BTW I made some lab measurements a few years ago that were consistent with Kelly's paper (assuming the matching data from TSMC was accurate).

Rob is probably right about the kT/C driving the cap size. That is usually the case in my designs (which is why I like the pure 1.5-bit/stage architecture so much). Be careful when calculating kT/C requirements for your converter as there are a lot of mistakes in the literature.

Murmann (he's a helpful guy!) has an excellent tutorial on calculating noise in a switched-cap amplifier the right way:

"Thermal Noise in Track-and-Hold Circuits: Analysis and Simulation Techniques" in IEEE Solid-State Circuits Magazine, June 2012

Title: Re: Relaxing the matching requirement in first stage of Pipeline ADC
Post by SNIKE on Aug 1^st, 2014, 11:13am

Hi Carl,
I decided to use digital calibration. My simulations show that for noise purpose 0.5pF is Ok [ need 2pF in total ].

Rob do you have any pointers to calibrating 1.5Bit system? I found Karnicolas Calibration very simple. I am looking for using Karnicolas technique for 1.5Bit system.
I don't want a complex calibration scheme like background calibration or calibrating finite OTA gain.

Yes I am following Murmann's method. He was my Professor :)

Title: Re: Relaxing the matching requirement in first stage of Pipeline ADC
Post by SNIKE on Aug 1^st, 2014, 11:15am

Sorry *carl :)

Title: Re: Relaxing the matching requirement in first stage of Pipeline ADC
Post by RobG on Aug 1^st, 2014, 11:16am

Dagnabbbit Carl, now I'll spend the weekend thinking about this instead of sleeping peacefully ;)

Title: Re: Relaxing the matching requirement in first stage of Pipeline ADC
Post by RobG on Aug 1^st, 2014, 11:28am

SNIKE wrote on Aug 1^st, 2014, 11:13am:

Rob do you have any pointers to calibrating 1.5Bit system? I found Karnicolas Calibration very simple. I am looking for using Karnicolas technique for 1.5Bit system.
I don't want a complex calibration scheme like background calibration or calibrating finite OTA gain.

Yes, listen to Carl on the subject of calibration. ;) He actually has done a lot of work on the subject.

Title: Re: Relaxing the matching requirement in first stage of Pipeline ADC
Post by carlgrace on Aug 1^st, 2014, 3:18pm

Thanks for the kind words Rob. Do think it through... I've had many a sleepless night thinking about this stuff over the years.

SNIKE:

The Karanicolas algorithm is the way to go. I've used it on several converters. Only do background or nonlinear calibration when you have to... it's MUCH more complicated. BTW, the Karanicolas algorithm *does* correct for finite opamp gain, just not for non-constant opamp gain.

in it's original form, the Karanicolas algorithm is only applicable to stages with a single decision level (he used stage gain less than two to get redundancy).

Soenen extended the algorithm to converters using redundant signed digits technique (like 1.5b/stage). I recommend you use that.

The paper is: Soenen and Geiger, An Architecture and An Aglorithm for Fully Digital Correction of Monolithic Pipelined ADCs IEEE TCAS-II March 1995

Main mistake I see new designers make is in their reference design. remember an error in your reference is the same as an error in your MDAC. Make sure you design the reference buffers carefully and simulate them!

Title: Re: Relaxing the matching requirement in first stage of Pipeline ADC
Post by carlgrace on Aug 11^th, 2014, 9:26am

RobG wrote on Aug 1^st, 2014, 11:16am:

Dagnabbbit Carl, now I'll spend the weekend thinking about this instead of sleeping peacefully ;)

It's time to swallow my pride and agree with Rob now.

He's right about the matching requirement on the DAC capacitors. I went through it this weekend and convinced myself the DAC linearity has to be at least as accurate as the current and downstream stages. So, for a 14-bit ADC, the first-stage DAC has to be 14-bit linear regardless of how many bits you convert. You were right, Rob.

That said I think the confusion arose because I tend to use 1.5-bit stages whenever possible. In a 1.5-bit stage, the DAC is inherently linear in a differential sense so the cap matching only affects the closed-loop MDAC gain. There the requirement DOES relax if you have a multi-bit stage. So, while a multi-bit stage won't relax your cap matching requirement, it will relax your open-loop opamp gain requirement.

Hope you didn't lose too much sleep, Rob! ;)

Title: Re: Relaxing the matching requirement in first stage of Pipeline ADC
Post by RobG on Aug 11^th, 2014, 10:15am

Oh man, we passed each other on the road to learning! I did lose a lot of sleep and tried an analysis and was going suggest the answer was sqrt(Rob*Carl). Don't worry, I hardly sleep these days anyway.

I was so tired I'm not sure what my notes mean, lol, but I think I found with 1.5 bits/stage the cap matching just affects the gain like you just said so we now agree there. However, if you do 2.5 bits/stage the requirements drop by sqrt(2) assuming you keep the total cap value the same (so I was wrong there - but this is what Kelly's paper says). This seems to indicate he'd need 12 bit matching for 1.5 bit/stage (what next stage errors!). 11.5 bit matching for 2.5 bits/stage, and 11 bit matching for 3.5 bits/stage, etc.

I don't know.. the analysis isn't super easy and the next stage adds errors too. It is easy to overlooking something so a good model is essential.