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Design >> Analog Design >> Dynamic Latch Comparator
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Message started by farsheed on Aug 1^st, 2014, 11:16am

Title: Dynamic Latch Comparator
Post by farsheed on Aug 1^st, 2014, 11:16am

Hi all,

I want to know that, propagation delay is an important factor for designing a dynamic latch comparator. Can someone explain why the factor is so important and how much delay is expected/expectable as the output result?

Title: Re: Dynamic Latch Comparator
Post by carlgrace on Aug 1^st, 2014, 3:21pm

The propagation delay sets the maximum frequency of operation for the latch. You want the decision to propagate as fast as possible so you can clock the comparator as fast as possible.

How much delay is expected depends entirely on the process you are using.

Title: Re: Dynamic Latch Comparator
Post by farsheed on Aug 2^nd, 2014, 10:02am

Thanks for the reply. I am using CADENCE 0.18um process and I'm getting 4.2nS as the delay for my design. My design is able to run for 50MHz. Is this response ok?

Title: Re: Dynamic Latch Comparator
Post by carlgrace on Aug 4^th, 2014, 11:11pm

Probably but it depends on that you're using it for. It's not fast enough for a 50 MS/s pipelined ADC for example, but it could be fine for other applications.

Title: Re: Dynamic Latch Comparator
Post by RobG on Aug 6^th, 2014, 2:19pm

To expand... propagation delay isn't fixed - with small inputs it gets larger and larger. With a small enough input it won't trip in time and you will get an error. The problem is called metastability. You need to figure out how small an input you can handle and jump through some formulas to convert it to a bit-error-rate.

Designer's guide actually has a paper on it... http://www.google.com/url?sa=t&rct=j&q=&esrc=s&source=web&cd=1&cad=rja&uact=8&ved=0CB0QFjAA&url=http%3A%2F%2Fwww.designers-guide.org%2Fanalysis%2Fmetastability.pdf&ei=RZriU4XnKtThoAToloKgBA&usg=AFQjCNEJ6jRe3nlsP-erZX0DTxHo-GzOAw&sig2=BbYtrEn0cnUmm9NH3mmDvw&bvm=bv.72676100,d.cGU