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https://designers-guide.org/forum/YaBB.pl Design >> Analog Design >> Problem with non-overlap circuit https://designers-guide.org/forum/YaBB.pl?num=1407328536 Message started by AMSA on Aug 6th, 2014, 5:35am |
Title: Re: Problem with non-overlap circuit Post by boe on Aug 11th, 2014, 12:09am AMSA, if you use an inverting "delay line", you change the logic function - so the circuit can no longer work. If you think about the circuit you will see that the length of the delay line defines the duration of the both-off state. - B O E |
Title: Re: Problem with non-overlap circuit Post by AMSA on Aug 13th, 2014, 8:16am I see. But how do you suggest the delay line implementation? Isn't using NOTs? NOTs aren't made of inverters? I have seen this circuit around the web. But in one or two books too. Regards |
Title: Re: Problem with non-overlap circuit Post by carlgrace on Aug 13th, 2014, 2:03pm What do you mean "proximate" the rise and fall edges? The minimum you can reliably have for non-overlap depends on your process. So does the minimum rise/fall times. |
Title: Re: Problem with non-overlap circuit Post by boe on Aug 14th, 2014, 3:50am AMSA wrote on Aug 13th, 2014, 8:16am:
AMSA, but overall, the delay line needs to be non-inverting (i.e. have an even number of inverters). - B O E |
Title: Re: Problem with non-overlap circuit Post by AMSA on Aug 14th, 2014, 5:56am BOE, but that wasn't what I've made? If you notice on the circuit, the feedback is taken after 2 delays, that is, two inverter - so to say after an even number of inverters. Isn't correct? Well, the idea that I have after reading about his subject was that one can control the non overlap space by inserting a number of (EVEN) inverters on the feedback. That's correct. However, after I've done my readings, I put that into practice and I found that I canno't create an accurate delay (space between the signals) between the signals in a way that I can do it in a fine manner, that is, have something like a fine tune of the delay. I've enven tried with only two inverters (even) with small values of W/L, somsthing aroung 200n/160n and even though I didn't managed to get that fine tune of the delay. That's why I asked this here. Regards. |
Title: Re: Problem with non-overlap circuit Post by wendyyang100 on Aug 14th, 2014, 7:43pm Hi, I think the "fine tune delay" is not easy to get, since the delay of inverter strongly depends on the process. And the delay caused by layout may count sometimes. wendy |
Title: Re: Problem with non-overlap circuit Post by boe on Aug 15th, 2014, 5:06am AMSA, AMSA wrote on Aug 14th, 2014, 5:56am:
AMSA wrote on Aug 6th, 2014, 5:35am:
AMSA wrote on Aug 14th, 2014, 5:56am:
However, as already mentioned by carlgrace, there are fundamental limits what you can achieve in your process (and under your operating conditions), also in terms of accuracy (variance). - B O E |
Title: Re: Problem with non-overlap circuit Post by AMSA on Aug 15th, 2014, 12:18pm Ok BOE I understood why you said that. My mistake. Can you elaborate the charge and loading? So maybe I'm at the process limit, is that it? Perhaps I should have given the set of operating conditions and the process I am using: The non overlap circuit is operating @500Mhz; The process is 130nm from UMC; The transistors I am using are the 3.3V transistors; Regards. |
Title: Re: Problem with non-overlap circuit Post by boe on Aug 18th, 2014, 6:44am AMSA, in my tech, a straight-forward non-overlap circuit with 3.3V transistors (3.3V, 27 degC, typ. process) and 2 inverters can achieve a gap of about 200 ps. I am not sure it makes even sense to go below that to ensure proper operation over PVT corners. If you want to increase the gap, you can increase the load of (i.e. add cap to) internal nodes... - B O E |
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