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Design >> Analog Design >> LDO design
https://designers-guide.org/forum/YaBB.pl?num=1408351803

Message started by supermoment on Aug 18^th, 2014, 1:50am

Title: LDO design
Post by supermoment on Aug 18^th, 2014, 1:50am

Hi

Shall the pmos pass element in the LDO regulator operate in saturation region? why?
Sometime i did come across article saying it could operate in triode region to reduce the pmos size, something related to efficiency.
it is advisable?

Title: Re: LDO design
Post by raja.cedt on Aug 18^th, 2014, 2:15am

As long as you have enough loop gain regulator works from dc point of view but think about mid band PSRR..

Title: Re: LDO design
Post by supermoment on Aug 18^th, 2014, 4:05am

if the gain is still >60dB but at slow corner, the pmos might go into triode region due to larger vsg and smaller pmos size. Is it allowable?

Title: Re: LDO design
Post by AnilReddy on Aug 18^th, 2014, 5:41am

Hi supermoment,

If the size alone is your concern, you can keep the transistor in triode. However, it would increase the voltage swing at the gate which in-turn demands the design of the previous stage for higher voltage swings which may not possible. This situation is particularly worse when you have to supply highest load current at lowest supply voltage and at SS -40.

as raja.cedt pointed out, AC PSRR will get affected, because, if the transistor is in triode then vds will also control the current through the channel which will effect output voltage. This will happen at those frequencies where loop can no longer regulate the output voltage (happens roughly beyond unity-gain frequencies of the loop).

Any comments are welcome.

Bye.

Title: Re: LDO design
Post by supermoment on Aug 18^th, 2014, 7:34am

Hi
any good reference paper?

The previous stage of the pmos pass element is usually come with a buffer to provide 1/gm low resistance to push the pole to higher frequency right. Is this a common practice for pmos LDO?

Title: Re: LDO design
Post by raja.cedt on Aug 18^th, 2014, 2:08pm

Hello,
Buffer based design is quite common in older days but with lower supply buffer might be ended up in sub-threshold region but this is also okay to some level, this will give better psrr by isolating Cgs from the opamp being driven, watch out buffer current it is not negligible.. Plz refer the following pap...

A Transient-Enhanced Low-Quiescent
Current Low-Dropout Regulator With
Buffer Impedance Attenuation

Thanks,
Raj!!!

Title: Re: LDO design
Post by raja.cedt on Aug 18^th, 2014, 2:20pm

One more...

http://www.ece.ust.hk/public/activities/fyp/fyp07/poster_MP3-07.pdf

Title: Re: LDO design
Post by supermoment on Aug 18^th, 2014, 7:38pm

hi
Thanks for your info.

What is the current method??

I also find that the offset is relatively large during no-load condition as the gain is lower because vg net of the pmos is relatively higher.

Title: Re: LDO design
Post by supermoment on Aug 19^th, 2014, 7:19am

hi Raj,

in the off-state or no-load case, the pmos has no current flowing, it cause the gain to drop and the offset become large. How to resolve this scenario?

Title: Re: LDO design
Post by carlgrace on Aug 19^th, 2014, 10:41pm

LDOs usually have a "ground current" that is a current that goes through the resistive divider that generates the feedback signal.

If you're having stability problems at startup or in a low-current state you can resolve this by increasing the current through the feedback divider resistors. Obviously this reduces your efficiency but sometimes it is necessary.

Title: Re: LDO design
Post by supermoment on Aug 19^th, 2014, 10:55pm

hi Carlgrace,

Yes there is some amount of current in the divider. it did not help much as the pmos device is relatively large relative to the uA current. For example, full-load can be 100-200mA while no load can e 0A for external.

Many papers published the Q current is only 50uA or less in no-load . could it achievable across PVT?

Title: Re: LDO design
Post by carlgrace on Aug 20^th, 2014, 1:24pm

Yes it is achievable across PVT. It's a design issue. You have to design you op amp so it is stable at no load current. Simple as that. Increasing the current through the divider is kind of a cheap way to help you op amp, but you may have to look into how your compensating it.

Title: Re: LDO design
Post by raja.cedt on Aug 21^st, 2014, 1:56am

Hi,
I totally agree with carlgrace. Normally it's design problem and if you have to manage regulator from min to max current, Min is bad for stability and max bad for psrr. But in some cases you may have to support less range(40mA-100mA) and during power up it still has to work with no load(because load will take some time and it depends on chip start up sequence). In this I would normally go with some bleeder current which assures some current independent of load..

Raj!

Title: Re: LDO design
Post by supermoment on Aug 21^st, 2014, 3:39am

yes i know bleeder can solve the problem at the cause of power.
However in many papers, it claim low Q current which is <50uA current. Their efficiency is near to 99%. Is that true?

for example the Raja point out:
http://www.ece.ust.hk/public/activities/fyp/fyp07/poster_MP3-07.pdf
the Q current is only 55uA and efficiency is 99.9%

Title: Re: LDO design
Post by raja.cedt on Aug 21^st, 2014, 6:27am

hello,
Efficiency depends on current and drop out....

Different regulators have different kind of priorities, Some regulators have external cap based (mostly power management) where efficiency matters a lot, few are internal to chips like they only drive a pll or even small VCO where Midband PSRR are is very critical and efficient may not be that high priority.