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https://designers-guide.org/forum/YaBB.pl Design Languages >> Verilog-AMS >> Verilog-A Model https://designers-guide.org/forum/YaBB.pl?num=1408367309 Message started by bki on Aug 18th, 2014, 6:08am |
Title: Verilog-A Model Post by bki on Aug 18th, 2014, 6:08am Hi, i never worked with Verilog-A before and now i try to add a model in cadence. I always get errors that i don´t really understand. Maybe someone can help me to correct the model. It should be a 2 Input AND Gate. Thats the Code: `include "constants.vams" `include "discipline.h" module V_and(in,out); parameter real size = 2 from [2:inf), vout_high = 5, vout_low = 0 from (-inf:vout_high), vth =1.4, tdelay = 5n from [0:inf), trise = 1n from [0:inf), tfall = 1n from [0:inf); input[0:1] in; output out; voltage in,out; integer in_state[0:1]; integer out_state; integer i; real vout; analog begin @(initial_step) for(i=0;i<2;i=i+1) in_state[i]=0; generate i (0,1) begin @(cross(V(in[i])-vth)) begin in_state[i] = V(in[i])>vth; out_state=1; for(i=0;i<2;i=i+1) if(!(out_state && in_state[i])) out_state=0; if(out_state) vout=vout_high; else vout=vout_low; end end V(out) <+ transition(vout,tdelay,trise,tfall); end endmodule The Errors are: Line 35: "@(cross(V(in[i]<<--?)-vth))" : Identifier ("in") is neither and array nor a vector. Declare identifier as an array or a vector. :The node array access is out of range. Correct the problem. Line 30: Encountered an invalid assignment during `generatre`or `genvar`unrolling. Check the validity of the genvar variables. |
Title: Re: Verilog-A Model Post by boe on Aug 18th, 2014, 7:01am bki, First of all, it is recommended to use genvar instead of generate. Secondly, you should define in as a bus both in the input declaration and in the voltage declaration. - B O E PS: please use [ code ] [ /code ] (without the spaces) to enclose code. |
Title: Re: Verilog-A Model Post by cheap_salary on Aug 18th, 2014, 7:13am `include "constants.vams" `include "discipline.h" module V_and(in, out); input [0:1] in; voltage [0:1] in; output out; voltage out; parameter real size = 2 from [2:inf), vout_high = 5, vout_low = 0 from (-inf:vout_high), vth =1.4, tdelay = 5n from [0:inf), trise = 1n from [0:inf), tfall = 1n from [0:inf); integer in_state[0:1]; integer out_state; integer j; real vout; genvar i; analog begin @( initial_step ) begin for(j=0; j<=1; j=j+1) begin in_state[j] = 0; end //for end //initial_step for(i=0; i<=1; i=i+1) begin @( cross(V(in[i])-vth) ) begin in_state[i] = V(in[i]) > vth; end //cross end //for out_state = 1; for(j=0; j<=1; j=j+1) begin if(!(out_state && in_state[j])) out_state = 0; end //for if(out_state) begin vout = vout_high; end else begin vout = vout_low; end //if V(out) <+ transition(vout, tdelay, trise, tfall); end //analog endmodule |
Title: Re: Verilog-A Model Post by bki on Aug 18th, 2014, 7:31am It works! Thank you!!! |
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