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Design >> RF Design >> VCO Design
https://designers-guide.org/forum/YaBB.pl?num=1413578972

Message started by AZADBAKHT on Oct 17^th, 2014, 1:49pm

Title: VCO Design
Post by AZADBAKHT on Oct 17^th, 2014, 1:49pm

Hi all
i want to design LC-VCO in 8-12 Ghz (X Band).
so i designed a LC-VCO without switch Capacitor and obtained 3G Kvco in simulation.also i designed this VCO with Switch Capacitor and obtained 250-400 M Kvco in simulation.
now i need to know,can i use this two design in pll!
whats your opinion? can i do it?
thank for your attention.

Title: Re: VCO Design
Post by tm123 on Oct 19^th, 2014, 8:38am

Hi AZADBAKHT,

High Kvco like this will likely result in high VCO phase noise and high PLL spurs. Of course it depends on what your specs are but I consider 100MHz/V Kvco as high, so I would look at other design techniques to reduce it.

Tim

Title: Re: VCO Design
Post by raja.cedt on Oct 19^th, 2014, 8:50am

Hi,
As Tim said it all depends on your phase noise requirements. But in general for serial IO applications 800Mhz/V is okay at least for the all the standards below 8Gbps. Where as in case of wireless people say it's too high.
Higher Kvco increase noise from loop filter(but this is very less compared to VCO,CP noise), this makes your vco very sensitive to power supply noise.

Have a proper estimations for the final jitter/phase noise.

Thanks,
Raj.

Title: Re: VCO Design
Post by AZADBAKHT on Oct 19^th, 2014, 10:10am

ok
Thank a lot sir Tim.

Title: Re: VCO Design
Post by AZADBAKHT on Oct 19^th, 2014, 10:13am

ok
Thank for your attention sir Raj.