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Modeling >> Behavioral Models >> Modeling dependent current source.
https://designers-guide.org/forum/YaBB.pl?num=1417259413

Message started by anas.iftikhar on Nov 29^th, 2014, 3:10am

Title: Modeling dependent current source.
Post by anas.iftikhar on Nov 29^th, 2014, 3:10am

Hi,

How should I model a voltage-controlled-current source in Verilog-A?
Need help.

Regards.

Title: Re: Modeling dependent current source.
Post by Geoffrey_Coram on Jan 5^th, 2015, 1:04pm

What have you tried? How complicated is the equation?

This is a vccs:

I(a,b) <+ V(c,d);