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https://designers-guide.org/forum/YaBB.pl Design Languages >> Verilog-AMS >> Verilog-A analysis() not working as expected https://designers-guide.org/forum/YaBB.pl?num=1420494569 Message started by danmc on Jan 5th, 2015, 1:49pm |
Title: Verilog-A analysis() not working as expected Post by danmc on Jan 5th, 2015, 1:49pm Hello, I am trying to implement a filter which has a sinc(f) frequency response or in otherwords, a rectangular pulse impulse response. I have implemented this with Code:
This works fine for transient analysis. However for PSS analysis (spectreRF) I get hidden state complaints. So I tried adding Code:
before the module line. That got rid of the complain and gave non-convergence. Then I tried adding: Code:
because I really don't care if this module is active during PSS but it is nice to not have to change netlists between PSS and transient sims. However, that also fails with a zero jacobian at the integ node (integrator output). That says to me that the analysis() bit isn't really doing what I thought. Any suggestions? Thanks -Dan |
Title: Re: Verilog-A analysis() not working as expected Post by Geoffrey_Coram on Jan 7th, 2015, 5:28am When you say "that also fails with a zero jacobian" is that during the PSS or transient? I'm guessing it's during PSS, when analysis("pss") is true, and your module has no contributions in that case. Is there a dc path from the integrator output through the rest of the circuit in that case? Or could you add contributions to force V(out) to zero for PSS, if you don't care what it does? |
Title: Re: Verilog-A analysis() not working as expected Post by Geoffrey_Coram on Jan 7th, 2015, 5:36am I do have to say: I avoid absdelay() and analysis() -- they make no sense for compact modeling, which is most of what I do with Verilog-A. And I prefer ddt() to idt(). analysis() is tricky: what does analysis("pss") return if you're in the initial transient (tstab) of a PSS? And you'd need to handle qpss and hb also -- there's no generic string like "any pss-like analysis" to get all the analyses that care about hidden state without listing them individually. Also, absdelay() is probably expensive to implement correctly. Each time the module is evaluated, you get a new value for V(integ), so each point in the delay line has a different delay and the simulator has to track all of them. |
Title: Re: Verilog-A analysis() not working as expected Post by Geoffrey_Coram on Jan 7th, 2015, 5:38am Geoffrey_Coram wrote on Jan 7th, 2015, 5:28am:
Actually, it must be the two internal nodes: Code:
which have no contributions at all during pss, and thus are just floating. |
Title: Re: Verilog-A analysis() not working as expected Post by danmc on Jan 30th, 2015, 6:27am Geoff, you're right. It was the lack of contributions in pss mode. That fixed this model. Thanks! -Dan |
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