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Design >> Analog Design >> SC Common Mode Feedback
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Message started by Schligger on Jan 7^th, 2015, 12:18pm

Title: SC Common Mode Feedback
Post by Schligger on Jan 7^th, 2015, 12:18pm

Hi everyone,

I'm working on a fully differential OTA (folded cascode) and have a question about the switched-capacitor common mode feedback.
A similar circuit is shown in the appendix. It only shows the half circuit of the OTA.
There, bias voltage "BiasE" is the desired output common mode voltage. In my case, this is generated by a resisitve voltage divider and equal to half of the supply voltage.
I haven't found anything in literature about the initial value of "V_CMC". If i don't care about it, the tail current of the OTA isn't really well defined during Clock-Phase PHI1.
(when capacitors Ca are precharged to the desired output common mode voltage, decoupled from Capacitors Cb).

Does this any matter?
I would also connect "CMC" to "BiasA" during this phase, but I'm not sure if it's the right way.

Has somebody already desinged such a SC-CMFB and could help me?

Thanks a lot

Title: Re: SC Common Mode Feedback
Post by carlgrace on Jan 12^th, 2015, 10:47am

The tail current of the OTA is defined just fine during phi1. You can think of the CM feedback circuit as a first-order low pass filter. So, during Phi1 the voltage on the cap connected to the tail current source doesn't change much. It takes many clock cycles to change it a lot.

The initial condition of V_CMC doesn't matter. It will take a few cycles to settle... it doesn't stabilize the common-mode output of the OTA infinitely fast. How many clock cycles it takes depends on the capacitor values you use and what they are relative to other capacitiances in your circuit).

Title: Re: SC Common Mode Feedback
Post by Schligger on Jan 12^th, 2015, 3:19pm

Thanks carlgrace,

the problem is that i don't want to spend much time on setting the common mode. The amplifier is just turned on, amplifies the residual voltage (from 1st stage of a pipeline ADC) and after that it's turned off again. So I'd like to set the common mode within one cycle. Till now it looks like it's working if i connect "CMC" to "BiasA" during initialization.

Title: Re: SC Common Mode Feedback
Post by carlgrace on Jan 12^th, 2015, 4:25pm

OK, so you're doing a non-standard design where you're shutting down the amplifier between clock phases to save power? Perhaps you'd be better off using a "switched ota" approach to the ADC.

Title: Re: SC Common Mode Feedback
Post by Schligger on Jan 13^th, 2015, 1:54am

Does "Switched OTA" mean that I could share the OTA to the different stages of the pipeline? That won't work ;) Because in the end, this "pipeline"-ADC juct consists of two stages, employing SAR-ADCs as SUB-ADC.

And yes, I want to turn it of to save power, because it needs much power to meet the noise specifications.

Title: Re: SC Common Mode Feedback
Post by carlgrace on Jan 13^th, 2015, 10:38am

No switched OTA is a low-power approach where instead of using switches the OTA itself is powered down between cycles. It works and there are some papers about it if you search for them.

If you're really concerned about the common-mode settling time you can look into using a continuous-time CMFB. The downside is it uses a bit more power (but not a lot) and it can have issues with swing. The upside is it does need to settle over several cycles like the SC CMFB.

I've never tried exactly what you're doing but even if you precharge the tail current source like you're suggesting I suspect you're going to get enough charge injection that you may still need to wait a couple of cycles for it to settle out.