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Design >> Analog Design >> Folded Cascode topologies confusion
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Message started by AMSA on Feb 1^st, 2015, 9:15am

Title: Folded Cascode topologies confusion
Post by AMSA on Feb 1^st, 2015, 9:15am

Hi guys, I have a question on folded cascode topologies.

We can choose between NMOS or PMOS mosfets for the input in the differential pair.

As we can see in several books, if we choose NMOST for the input in the differential pair, the current mirror on the cascode side is chosen to be NMOS. They can be a simple current mirror or a cascode current mirror. Since the topology presents a cascode (above) we choose the cascode current mirror too. That cascode current mirror can be simple or wide-swing.

So far so go.

What concerns to the PMOST for the input differential pair, the same applies but now the current mirror is above and the cascodes are in he lower side. The same applies here when it comes to choose the type of current mirror.

Those are the traditional folded cascode topologies. They come in almost all book in electronics.

However, I have seen a topology, where, for example, with PMOST in the input differential pair that the cascode current mirror is from a NMOS type and not PMOS, as it should, from my understanding and from what I have seen in books.

I did some more research and I saw that there are lots of handouts in some universities and in one book (BAKER's book) where they used this PMOST in the input differential pair and the current mirror with NMOST cascode. For example, in Baker's book, he has in page 803 (or something - 3rd Edition) a folded cascode amplifier with NMOST in the diff. input pair and the cascode current mirror with PMOST.

Can someone explain me what are the major or simply the differences between the "traditional" folded cascode and this kind of modified folded cascode version of the "traditional" folded cascode amplifier?

Drawback, advantages, major differences in performance, etc.

I can let here some pictures for reference:

Kind regards and thank you in advance.

Title: Re: Folded Cascode topologies confusion
Post by raja.cedt on Feb 3^rd, 2015, 2:39am

Hi,
Interesting observation..
1. They are very similar except very high frequency. In the traditional structure diff pair current divides equally because of equal impedance at M5,M7 sources. Where as in baker book they may not be equal because of the diode connect impedance is much lesser than1/gm. Two asymmetric paths means high frequency Pole-Zero doublets.
2. In baker opamp diff pair tail current and cascade could share a bias line where as in traditional one you need one more (as you can't share), but this may give some oscillations as you could find a week +ve fb.

Thanks,
Raj.

Title: Re: Folded Cascode topologies confusion
Post by Rakesh on Feb 4^th, 2015, 8:37am

Hi,
Interesting question. Lets see the cadence figure for analysis.
In traditional folded cascode, both the pmos side and nmos side carries the signal current (gm deltaV/2) and hence can be sized accordingly. However in the modified folded cascode (ref to cadence figure)
1. Top pmos can be assumed to be constant current sources. The transistor M35 should contribute to gm deltaV/2 and we inject gm deltaV/2 at source of M25. Hence transitor M25 should carry gmdeltaV current which is different from traditional folded cascode. Hence it has to be sized higher. This can lead to higher parasitic capacitance and lower output impedance. Sometime this can dominate for Dc gain.
Rakesh

Title: Re: Folded Cascode topologies confusion
Post by RobG on Feb 9^th, 2015, 5:11pm

The design concept exemplified by the cadence schematic has been around for a long time, see Hogervost's paper in Dec 1994 JSSC.

It is my preferred topology and I expect it would be taught more if the mirror wasn't so nonconventional. It has a PMOS diff pair which is usually lower noise; the mirror active devices are NMOS, and they are faster; the signal has to travel through less devices; and the PMOS current source can be high impedance and low noise since it doens't have to pass the signal. The one thing I would do different in your schematic is to use an NMOS second stage to remove the systematic offset and to first order cancel power supply effects on the mirror.

Note that for minimum noise you can just use resistors in place of NM34 and 35 (and diode connect NM23). That was done back in the stone age when cavemen were forced to use bipolars without a decent pnp. This mirror is a circuit you will want to keep in the back of your mind as it has many uses. Also in the "must know" category is the class AB output stage described in the paper I referenced. I can't believe I'm old enough to remember when the paper first came out. :-/