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https://designers-guide.org/forum/YaBB.pl Design Languages >> Verilog-AMS >> To Model a RC circuit in verilogA and feed the settling time. https://designers-guide.org/forum/YaBB.pl?num=1423128208 Message started by siloo_newbie on Feb 5th, 2015, 1:23am |
Title: To Model a RC circuit in verilogA and feed the settling time. Post by siloo_newbie on Feb 5th, 2015, 1:23am Hi, I am beginner who is trying to model a RC series circuit using verilogA in cadence environment. I have coded as below, where the resistance is modeled as switch through ON and OFF resistance. input in, clk, vss; output out; electrical in, clk, vss, out; parameter real clkThreshold = 0; parameter real Cload = 7e-12; parameter real Ron = 1; parameter real Roff = 100M; analog begin if(V(clk) > clkThreshold ) begin V(in,out) <+ Ron * I(in,out); end else begin V(in,out) <+ Roff * I(in,out); end I(out, vss) <+ ddt(Cload * V(out,vss)); end Using RC charging formula, Vout = Vsupply (1-e pow(-ts/RC) ) Where Vout = output voltage Vsupply = supply voltage (I think, in our case it is input voltage ?) ts = settling time R = Ron = on resistance C = Cload = load capacitance. The question is how to incorporate this formula to above verilogA code and then find the Cload value by giving ts as an inputs ? Hope the question is some what clear (for now i not worried about the discharging ) !! Kindly help me out here :'( |
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