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Design >> RF Design >> Class B Power Amplifier
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Message started by Dshoter on Mar 19^th, 2015, 1:35pm

Title: Class B Power Amplifier
Post by Dshoter on Mar 19^th, 2015, 1:35pm

Hi. I'm trying to design a Class B Power Amplifier in CMOS. What do you guys think is the best approach to a successful design?
Start with the input and output matching networks? Check stability?
And If the PA is unstable, what to do?

Thank you.

With best regards.

Title: Re: Class B Power Amplifier
Post by aaron_do on Mar 20^th, 2015, 12:35am

Quote:

What do you guys think is the best approach to a successful design?

Hi,

your question is too broad. Your question is more likely to be answered if it something specific. Also, PA designs will be quite different depending on the application so you might want to give some details.

In terms of having a successful design (I'm just gonna assume you're new to this), some of the keys which I find useful are:

1) Make sure your final testbench represents the actual measurement setup as accurately as possible in order to get good correlation.

2) Make sure to test start up conditions using transient analysis. i.e. Ramp the supplies.

3) Make the design highly tunable. That means current biasing, digitizable tank caps etc.

4) Model your traces. In a high power design, even a relatively short trace can affect matching. Model the effects of nearby traces too. Couping to metal loops such as ground loops can de-Q your inductors.

5) For PA design in particular, pay attention to breakdown. That includes everything from transistors to metal traces, resistors etc

Perhaps the most critical part of the design will be the load transformation network. So that's a good place to start.

regards,
Aaron

Title: Re: Class B Power Amplifier
Post by Dshoter on Mar 20^th, 2015, 10:28am

aaron_do wrote on Mar 20^th, 2015, 12:35am:

Quote:

What do you guys think is the best approach to a successful design?

Thank you very much. I already designed some of the parts of the system. Now I'm having trouble to stabilize the Mosfet. I'm working with 0.13um at 2.4GHz, and I'm, targeting 20dBm (my Idmax is about 550mA).
I'm trying to stabilize the PA, but I'm having troubles at it. If I introduce some series resistance at the gate, It has to be quite high to put the PA in stable conditions, but my gain is dropping to much.. I think that the problem is from the Cgd cap that is feedbacking.. It would be nice to know how to measure this capacitances, so I could do a more extensive theoretical analysis..

With best regards.

Title: Re: Class B Power Amplifier
Post by aaron_do on Mar 20^th, 2015, 11:25pm

Quote:

I think that the problem is from the Cgd cap that is feedbacking.. It would be nice to know how to measure this capacitances, so I could do a more extensive theoretical analysis..

Hi,

if you already know the different components of your capacitance - overlap capacitance, channel capacitance, and parasitic capacitance - then you can get the values from a DC analysis and a layout parasitic extraction. However, the capacitance is changing over the operating point, so you could also get a lumped value by assuming your own model for the transistor (for example Cgs,Cgd, Cds, gm, r0, rg...), and running simulations (PSS + PSP probably).

cheers,
Aaron

Title: Re: Class B Power Amplifier
Post by Dshoter on Mar 23^rd, 2015, 2:03pm

When I measure my I-V characteristic, I see that when VDS is about 1.2V (my VDD) I have my maximum current. Lets say that that current is about 400mA.. It means that I have to transform my Rl to a proper value that is given by Ropt = 2*(Vdd-Vth)/Imax, where Imax is about 400mA, rigth?