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Design >> Analog Design >> How much of the charge pump current should be used for a PLL
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Message started by zczc999 on Mar 27^th, 2015, 4:48am

Title: How much of the charge pump current should be used for a PLL
Post by zczc999 on Mar 27^th, 2015, 4:48am

Hello,

I am new to PLL design. I have a question that which level of charge pump current is suitable for a pll.

I know the current should meet the requirement of bandwidth, damping, etc. But which order of magnitude is preferable, say 10uA, 20uA, 50uA, or 100uA, considering matching, noise. Now I am using a 15uA charge pump, I don't know if it is too small.

And the current has glitches at the edge of switching signals. The glitch is about 30uA. Will this has big affect on phase noise?

BTW, to eliminate the deadzone of PFD, a delay will insert at the reset path. Usually how much delay is added? I think the smaller the better, as long as the pulse can turn on/off the switches, so I am using about 200ps. Am I right?

Thanks

Title: Re: How much of the charge pump current should be used for a PLL
Post by Ken Kundert on Mar 27^th, 2015, 2:58pm

The charge pump current directly affects the gain of the loop, and hence its stability. Among any other constraints, the charge pump current is chosen to satisfy stability requirements.

-Ken

Title: Re: How much of the charge pump current should be used for a PLL
Post by loose-electron on Mar 27^th, 2015, 8:53pm

Charge pump current is interactively traded off against loop filter parameters. Higher currents mean bigger loop filter capacitors.

Now, what happens, is that the charge pump current can be scaled so that the charge injection of the current steering switches is insignificant in comparison to the charge pump current.

Title: Re: How much of the charge pump current should be used for a PLL
Post by weber8722 on Apr 21^st, 2015, 11:43pm

Hi,

all your questions are good questions! Best orient on a working design. Higher Icharge allows bigger C for same time-constant and thus lower noise. But if your osc is not low-noise too (like a simple ring-osc instead of LC osc with high-Q elements), then an over-design in CP makes little sense.
The first decision is probably also wether C of PLL loop filter is on-chip or off-chip. For on-chip you are typically anyway quite limited.

Collect all your specs, and discuss them with an expert + compare them to well-documented commercial PLL designs.

At CP output you usually see the wanted pulse current but together with a spike which often comes from Cgd of switching transistors. Often it matters not much, but adding a cascode can help - also for more constant output current vs Vout.

Optimize you CP + PFD togther over PVT corners + MC, then you should see how much margin is needed, better a bit more.

Bye Stephan