Title: How to use the example project having d2a?
Post by ruwan2 on Mar 27th, 2015, 8:49pm
Hi,
I find the below code on line. When I load it as a project to SMASH, I do not see the function of d2a. If d2a is excluded from the project, it can be loaded to the EDA software. I suspect that d2a has rule on net 'b' between buffer and resistor. Is it right?
Do I need to add more code?
Could you explain it to me?
Thanks,
Code:
`include "disciplines.vams"
connectrules my_connectrules; connect d2a; endconnectrules |
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Code:
`timescale 1ns / 10ps `include "disciplines.vams"
module testbench (); electrical gnd; ground gnd;
reg clk; initial clk=0; wire b;
always begin #10 clk=1; #10 clk=0; #10 clk=1'bx; #10 clk=0; #10 clk=1'bz; end
buffer buf0 (b, clk); resistor #(.r(100k)) r0 (b, gnd); endmodule
module buffer (out, in); output out; input in;
assign out = in; endmodule |
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Code:
// Logic to Electrical Connect Module // // Version 1a, 1 June 04 // // Olaf Zinke // // Downloaded from The Designer's Guide Community (www.designers-guide.org). // Post any questions on www.designers-guide.org/Forum. // Taken from "The Designer's Guide to Verilog-AMS" by Kundert & Zinke. // Chapter 4, Listing 18.
`include "disciplines.vams" `timescale 1ns / 10ps
connectmodule d2a (out, in); parameter real v0 = 0.0; // output voltage for a logic 0 (V) parameter real v1 = 5.0; // output voltage for a logic 1 (V) parameter real vx = 2.5; // output voltage for a logic x (V) parameter real vz = 5.0; // output voltage for a logic z (V) parameter real r0 = 1k from (0:inf); // output resistance for a logic 0 (Ohms) parameter real r1 = 1k from (0:inf); // output resistance for a logic 1 (Ohms) parameter real rx = 100 from (0:inf); // output resistance for a logic x (Ohms) parameter real rz = 1M from (0:inf); // output resistance for a logic z (Ohms) parameter real tr=1n from [0:inf); // rise time (s) parameter real tf=1n from [0:inf); // fall time (s) input in; output out; logic in; electrical out; real v, r;
assign in = in;
initial begin case(in) 1'b0: begin v = v0; r = r0; end 1'b1: begin v = v1; r = r1; end 1'bx: begin v = vx; r = rx; end 1'bz: begin v = vz; r = rz; end endcase end
always @in begin case(in) 1'b0: begin v = v0; r = r0; end 1'b1: begin v = v1; r = r1; end 1'bx: begin v = vx; r = rx; end 1'bz: begin v = vz; r = rz; end endcase end
analog V(out) <+ transition(v, 0, tr, tf) + transition(r, 0, tr, tf)*I(out); endmodule |
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