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https://designers-guide.org/forum/YaBB.pl Design Languages >> Verilog-AMS >> how to use "mixedsignal;" https://designers-guide.org/forum/YaBB.pl?num=1427607170 Message started by ruwan2 on Mar 28th, 2015, 10:32pm |
Title: how to use "mixedsignal;" Post by ruwan2 on Mar 28th, 2015, 10:32pm Hi, I see the following code on LRM. I do not see "mixedsignal" defined. Whether "mixedsignal" is a reserved word? Could you explain it to me? Thanks, Code:
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Title: Re: how to use "mixedsignal;" Post by Ken Kundert on Mar 30th, 2015, 11:57am You are defining the name mixedsignal. It should be included as a top-level module when running the simulation so that verilog knows which connect modules to use. When asking for help, you should make it easier for people to help you by formatting your code so that it is readable. The lack of indenting in your code makes it unnecessarily difficult to read. -Ken |
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