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https://designers-guide.org/forum/YaBB.pl Design Languages >> Verilog-AMS >> Question about two branches for a diode model https://designers-guide.org/forum/YaBB.pl?num=1428675643 Message started by ruwan2 on Apr 10th, 2015, 7:20am |
Title: Question about two branches for a diode model Post by ruwan2 on Apr 10th, 2015, 7:20am Hi, When I read the following example on AMS, I am puzzled about two branches for two terminals. What relationship of these two branches i_diode, junc_cap ? A diode should have one current flow through, what about the two current? Thanks Code:
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Title: Re: Question about two branches for a diode model Post by ruwan2 on Apr 10th, 2015, 8:08am Excuse me. I understand now. The capacitor is parallel with the diode. Thanks |
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