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Design >> Analog Design >> DRC: Triple well tie down
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Message started by philip_the_reverse on May 13^th, 2015, 2:38am

Title: DRC: Triple well tie down
Post by philip_the_reverse on May 13^th, 2015, 2:38am

Can anyone clarify what is the Triple well tie down rule, and how to avoid it.

It reads as below:

(Isolated pwell touching gate) must touch RX
which is electrically connected to (RX over NW) through M1.
notes3 This rule does not cover 5VHVFET