The Designer's Guide Community Forum

The Designer's Guide Community Forum
https://designers-guide.org/forum/YaBB.pl
Design >> Analog Design >> Question regarding a sawtooth circuit
https://designers-guide.org/forum/YaBB.pl?num=1432630070

Message started by AMSA on May 26^th, 2015, 1:47am

Title: Question regarding a sawtooth circuit
Post by AMSA on May 26^th, 2015, 1:47am

Hi guys,

I'd like to ask you a question regarding how a detail from a sawtooth circuit works. The circuit is the following presented in the figure

Suppose that this is already the steady-state.

The current source starts to charge the capacitor until its voltage reaches the VH. When he reaches this value the comparator toggles and the capacitor starts to discharge. Now the doubt is here: How the sawtooth starts to rise again? For example, there is another topology where one uses two comparator where each of them establishes each of the leading and trailing edges, that is, the amplitude of the comparator, when the capacitor will start to charge and discharge.

In this case, there is no second comparator to establish the low voltage threshold. So my question is, how with only one comparator, he manages to start charging again the capacitor.

Regards and thank you in advance.

Title: Re: Question regarding a sawtooth circuit
Post by RobG on May 26^th, 2015, 6:57pm

That isn't how I've seen it operate. The NMOS is supposed to be a switch that turns on when the voltage ramps to Vh. The switch completely discharged the capacitor, but you need a delay in there so the capacitor is completely discharged before the comparator turns the switch back off.

That way it will ramp up until it gets to Vh, then it will discharge completely very quickly and the start ramping up again.

To ramp up and down would take another threshold and a way to change the polarity of the current, as you had guessed.

Title: Re: Question regarding a sawtooth circuit
Post by AMSA on May 27^th, 2015, 10:02am

Hi RobG. Thanks for the reply. How I could implement that delay? Do you have any reference on this?

By the way, if you notice, the NMOS turns on when the ramp hits the VH. Right?

Title: Re: Question regarding a sawtooth circuit
Post by RobG on May 27^th, 2015, 11:18am

The Johns and Martin text has a similar circuit under CMOS relaxation oscillators.

The delay is just an inverter string between the comparator and NMOS. Yes, the NMOS turns on when the ramp hits VH. It will stay on until the comparator goes low, which is why you need the delay, otherwise it will not complete discharge, or maybe even maintain the voltage at VH like a unity gain buffer since the feedback is negative.

Title: Re: Question regarding a sawtooth circuit
Post by AMSA on May 27^th, 2015, 11:48am

Hi RobG. Thank you for your quicl reply.

I see. It is what I though.

Well, the detail here, regarding the fact that the sawtooth doesn't reach 0V when discharging is what was confusing me.

I though that he didn't reach 0V due to the Vth of the switch. So it has nothing to do with that. Right? Well, I though that the ramp started to charge again because the NMOS switch has switched of because the driving signal was below Vth.

I will try on a minute the delay. This will change the frequency of the sawtooth waveform.

But tell me another thing. If I add the delay, how the sawtooth will discharge quickly if the driving signal of the NMOS switch will be ON for longer time? Hmmm, being ON for a longer time will give time to the sawtooth discharge quickly?

Regards.

Title: Re: Question regarding a sawtooth circuit
Post by AMSA on May 27^th, 2015, 12:05pm

RobG, I have increased the output stage of the comparator, from 2 to 10 (0.68um) with same size and I have increased a bit the switch size (5um). The result is this one:

If you notice, or not, I can tell you, the voltage never reach zero, but around 100mV. There is a dead-zone when the sawtooth discharges completly. It has to do with tha fact that I am giving too much delay?

EDIT:

I am sorry, but I have another result:

Now it has reached almost 0V (16mV) however, I am facing that phenomenon inside the circle.

What you think about this results?

Title: Re: Question regarding a sawtooth circuit
Post by RobG on May 27^th, 2015, 12:26pm

I'm guessing it doesn't go down to zero because the IR drop across the NMOS switch. You can make that bigger and also put an PMOS switch in series with the current source to turn it off.

Title: Re: Question regarding a sawtooth circuit
Post by AMSA on May 27^th, 2015, 12:47pm

Rob, if I insert the NMOS switch in series with the current source, the sawtooth doesn't work. I am using a PMOS current source, so maybe I could put that between VDD and the gate of the PMOS current mirror?

RobG, I tried to increase the NMOS switch (that discharge the capacitor) and this is what happens:

As you can see there is an effect when we increase the NMOS width. Any suggestion?

Thank you in advance.

Title: Re: Question regarding a sawtooth circuit
Post by RobG on May 27^th, 2015, 1:36pm

I meant a PMOS switch in series with the current source - you want to turn it off when the NMOS switch is discharging the cap.

I don't know what else is going on - I think you understand the principle so you'll have to ask yourself "how is it supposed to work?" and then figure out why it isn't working that way ;)

Title: Re: Question regarding a sawtooth circuit
Post by AMSA on May 27^th, 2015, 1:51pm

Yeah, sure ;) Thanks for the help.

Regarding the PMOS, I tried that, but the sawtooth waveform went crazy.

Allow me to add one more thing.

It make sense to say that it might be good to not start at 0V because the next block will be a comparator which will compare this signal with a error voltage. So, one can say actually that the sawtooth must be within the comparator input range right?