The Designer's Guide Community Forum

The Designer's Guide Community Forum
https://designers-guide.org/forum/YaBB.pl
Design >> Analog Design >> how to simulate the input offset voltage of op amp
https://designers-guide.org/forum/YaBB.pl?num=1432794645

Message started by adie_N on May 27^th, 2015, 11:30pm

Title: how to simulate the input offset voltage of op amp
Post by adie_N on May 27^th, 2015, 11:30pm

Hai!! Good day..

I am currently developed the three stage op amp using 130nm technology. Therefore, I am looking best approach how to simulate/measure the input offset of op amp. I found that there are two type configuration how to measure the offset. (1) using open loop configuration and (2) using unity (follower) configuration. when I used the open loop configuration, I got 3.77mV of offset and 1uV for unity(follower) configuration. I bit Confuse what configuration i should follow. Really appreciate if anyone can explain to me?
sorry for the inconvenient question.

Thank You
Adi

Title: Re: how to simulate the input offset voltage of op amp
Post by AMSA on May 28^th, 2015, 1:31am

Hi adie_N,

I think you have to measure it in open-loop configure, even because, the comparator is to be used in a open-loop configuration.

I don't know if that input offset is high or not, because I don't know where he will be used and what is the performance and specifications of it.

But in first place, assuming that you are doing correctly the offset measurement, that is, that you have a correct setup for the offset measurement, try to use a very small step in the DC analysis. For example, 1uV or 10uV. Don't forget to tighten the span of the dc sweep so that the simulation don't take too long.

Give the feedback after you try.

Title: Re: how to simulate the input offset voltage of op amp
Post by adie_N on May 28^th, 2015, 2:26am

Hai AMSA

Thank you for your advice.

I try to use the open loop configuration and scale down the step size from 1mV to 1uV and 10uV. As a result, the offset voltage has been reduced to 1.6uV for 1uV step size and 4.7uV for 10uV step size. What is the best step size that I should take? since the different step size produce the different offset?

Thank you

Adi

Title: Re: how to simulate the input offset voltage of op amp
Post by AMSA on May 28^th, 2015, 3:11am

Can you try a smaller step size? Imagine, 0.1uV just to compare.

Title: Re: how to simulate the input offset voltage of op amp
Post by adie_N on May 28^th, 2015, 4:29am

AMSA,

when I try 0.1u step size, the offset voltage is approximately 1.6uV. It is almost equal to 1uV step size but the difference value is around 20nV. Do you have any idea to conclude this situation? should I used 1uV step size as reference value? It is logical we have 1.6uV offset voltage?

Thank you

Title: Re: how to simulate the input offset voltage of op amp
Post by AMSA on May 28^th, 2015, 4:56am

Well, if it is the same value then the input offset is 1.6uV. This might have to do with accuracy vs resolution, but I don't know how to explain this. Maybe someone else can. I think it is a good value, but it will depend on the application.

Have you compared to similar works? To similar works that shows the input offset value.

Title: Re: how to simulate the input offset voltage of op amp
Post by loose-electron on May 28^th, 2015, 3:21pm

How are you modeling transistor mismatch?

Your differential pair in the front end of the op-amp will generally be the biggest part of the problem.

I would expect real world silicon to have an input offset anywhere from 1mV to 20 mV for a CMOS op-amp.

Your numbers are much too small.

Title: Re: how to simulate the input offset voltage of op amp
Post by AMSA on May 29^th, 2015, 5:59am

loose, he is simulating in a virtual world and in schematic.

Title: Re: how to simulate the input offset voltage of op amp
Post by RobG on May 30^th, 2015, 3:55pm

You are measuring systematic offset which either comes from asymmetries. 1uV is very low - the offset due to mismatch will be around two orders of magnitude higher.

Title: Re: how to simulate the input offset voltage of op amp
Post by loose-electron on May 30^th, 2015, 9:45pm

AMSA wrote on May 29^th, 2015, 5:59am:

loose, he is simulating in a virtual world and in schematic.

Yes but he is talking about putting it onto 130nm CMOS somewhere along the way, and systematic offset won't matter if the matching error offset is much larger.