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Design >> Analog Design >> current distribution in ESD problem
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Message started by dog1 on Jul 2^nd, 2015, 1:11pm

Title: current distribution in ESD problem
Post by dog1 on Jul 2^nd, 2015, 1:11pm

Hi everyone,

I have a problem about the current distribution in parasitic bipolar during ESD event. You can find in the attached picture a top view of an example circuit. it is a diode used for ESD event. the cathode is a deep nwell and the anode is an isolated pwell sits in the NEWLL. To avoid current crowding, the PWELL is connected at point A while the NWELL is at B. However, there is a parasitic PNP between pwell-nwell-substrate. Let's say, the pad is connected to the PWELL and NEWLL connected to GND. When there is positive ESD applied to the PWELL, the bipolar is also on. I wonder where the connection to the substrate should be so that current will not crowd. Does anyone have any idea about it?

I think it should not matter where the substrate will be connected, since the base-emitter junction of the PNP, which is not affected by the distrution of the collector, is evenly distributed acorss the current path, and evenly inject current into the base. The current is then picked up by the collector evenly. However, this is just some personal thought. Does anyone have any knowledge or experience about it?

THX!

Title: Re: current distribution in ESD problem
Post by loose-electron on Jul 6^th, 2015, 5:59pm

Your layout needs to be able to absorb injected currents on the order of 1-10 amps (yes AMPS) of current briefly.

Consequently you need large junction spaces, heavily contacted connections and large metal interconnects.

As a start - treat it as an IR problem and start looking at the resistance of every contact, junction and interconnect.

I/O cells are big for a reason, and the reason is ESD.