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Simulators >> Circuit Simulators >> Noise Margin Analysis for Dynamic Logic circuits
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Message started by ValarMorghulis on Jul 10^th, 2015, 9:32am

Title: Noise Margin Analysis for Dynamic Logic circuits
Post by ValarMorghulis on Jul 10^th, 2015, 9:32am

Hi,

I am trying do the noise margin analysis of a dynamic CMOS logic circuit (Domino) which is run by a clock signal. Now, what should be the procedure to do that? I am trying to follow something similar to standard method of measuring noise margin for an inverter using VTC curve.

Thank you for your time and co-operation!