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Simulators >> RF Simulators >> Multi-phase switched-capacitor sampled pnoise simulation
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Message started by zeynep on Jul 31^st, 2015, 3:34pm

Title: Multi-phase switched-capacitor sampled pnoise simulation
Post by zeynep on Jul 31^st, 2015, 3:34pm

Multi-phase switched-capacitor sampled pnoise simulation
Today at 9:23am Quote Modify Hello,

I want to simulate a 6-phase switched-capacitor circuit. However, I have 6 sets of the same circuit working as time-interleaved. Thus, if the frequency of the 6-phase waveform is f, the output sampling rate becomes fx6.

I want to simulate the sampled noise at the output. I am using pss+pnoise(timedomain). I have also read Ken Kundert's tutorial file, although it was very helpful it does not cover multi-phase options. My problem is that pss uses f as the clock frequency (since it is the lowest clk in the circuit) and thus sampled pnoise folds everything in f/2, and I see peaks at integer multiples of f. However, in reality my sampled noise will be folded in 6f/2=3f, there should not be any peaks until 6f. If I had a nice white noise at the output, I may somehow scale the noise but I also have some noise shaping due to the structure I am simulating. Is there a legitimate way of simulating multi-phase SC sampled noise, when real sampling frequency (6f) is faster than the f?

For my case noise shaping is sharp so the timedomain (sampled) noise and source (sampled) noise are close to each other (4% difference) at low frequencies. And I have extra peaks at f for the sampled noise, which I can simply ignore but I am not sure if this simulation is correct or not.

PS: I can always go with transient simulation and I will do it at the end but I do not want to waste time for transient simulations and averaged fft's during the design phase.

Thanks in advance!

Title: Re: Multi-phase switched-capacitor sampled pnoise simulation
Post by Ken Kundert on Jul 31^st, 2015, 8:01pm

Back before there was noise sampling built into SpectreRF we would have to add test circuitry to the circuit in order to compute the sampled noise or jitter for us. Specifically, we would use Verilog-A to add a limiter that only passes the signal within a small range of the threshold and clips it otherwise. It seems like you can use this idea. Add limiters to each of the 6 outputs and sum the result, and report the simple time-averaged noise of the 'sampled' sum.

Take a look at the attached pdf file. This is an excerpt from the previous version of the PLL jitter paper.

-Ken