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Design >> Analog Design >> Dummy poly vs dummy devices
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Message started by RobG on Aug 11^th, 2015, 6:31pm

Title: Dummy poly vs dummy devices
Post by RobG on Aug 11^th, 2015, 6:31pm

Hello folks... I'm working in 28nm TSMC and see that the devices come with the option for two dummy poly stripes. As you know, at smaller geometries you need dummy devices around critical transistors such as those used in current mirrors or you can get significant mismatch.

It got me wondering if these dummy poly stripes worked as well as actual devices. It would sure make matching the layout with the schematic a lot easier not having to post annotate the schematic with whole devices.

So, is having dummy poly enough or do you have to have the whole device?

This may be explained in one of the 90 documentation files that come with the PDK... if you guys know which one you can let me know too ;).

Title: Re: Dummy poly vs dummy devices
Post by Tako on Aug 13^th, 2015, 3:19am

I used dummy devices. All terminals of NMOSes connected to ground and PMOSes terminals connected to VDD.

However, if the foundry delivered such a solution it should make a trick. It all depends how devices are manufactured (what are the technology steps one after another). In case of two matched transistors, additional poly strips should ensure that environments for the outer boundaries of gate_1 and gate_2 are the same as for the inner boundaries of these gates (environment between gate_1 and gate_2):

dummy --- gate_1 --- gate_2 --- dummy

Without dummies polys you would have

??? ----- gate_1 --- gate_2 ------- ???

thus an etching can be different between gates comparing to the outer parts of the gates.

If you have a possibility, ask this question to your foundry Field Application Engineer (FAE) and let us know. :)