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Design Languages >> Verilog-AMS >> @cross event hitting zero exactly
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Message started by Geoffrey_Coram on Nov 2^nd, 2015, 8:05am

Title: @cross event hitting zero exactly
Post by Geoffrey_Coram on Nov 2^nd, 2015, 8:05am

I just read through the VAMS LRM 2.4, and I don't see it saying anything about what the cross event is supposed to do if the signal exactly hits zero. Suppose the value at the previous timepoint was less than zero and on this timepoint, the value is exactly zero: should the event be triggered, or does it not trigger until the value actually goes above zero?

With any non-zero expression tolerance, the value could be said to be negative or positive. I can imagine a pathological case where the event triggering changes the direction of the signal, so that if we say hitting zero triggers the event, then we get a signal that hits zero and turns around so that it never actually crosses (and hence the event should not have triggered) -- but if we say that hitting zero is not enough to trigger (the signal must actually cross), then the next timepoint could be beyond timetol from the actual crossing, and we would be upset that the triggering didn't happen when the signal hit zero.

signal hits zero and that's enough to trigger the event, it immediately turns around so and doesn't actually cross), but if the