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Design >> RF Design >> Analog PLL questions
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Message started by YYou on Dec 16^th, 2015, 7:10pm

Title: Analog PLL questions
Post by YYou on Dec 16^th, 2015, 7:10pm

Hello,

I am designing an analog PLL - mixer-type phase detector. The mixer is double-balanced structure. The output is converted to single-ended from differential by a current-mirror type topology. Then the output is a high-impedance node (in the middle of a current sink and current source). If I directly connect the output to a LPF that is the same as the one connected to a charge pump output (R+C//C), the whole loop can be treated as a type-II like PLL.

Another question is about the PLL stability. If the PLL is unstable, what do you expect to see if measuring the output signal spectrum ?

Thank you!

Title: Re: Analog PLL questions
Post by raja.cedt on Dec 17^th, 2015, 5:11pm

1. Please post schematic, if I am not mistaken, in your case Mixer is driving a current mirror means charge pump current depends on error hence loop gain and hence stability depends on phase error. So you have to evaluate Stability very carefully. Better check current corresponding to zero phase and max phase error and do the loop dynamics calculation.

2. Very interesting Question, I haven't simulated unstable loop. Answer depends on what level of instability.
A. If phase margin is poor(say 45deg), then peaking in the spectrum near the loop bandwidth, which makes integrated phase error worse.
B. If phase margin is very poor, means control voltage oscillates. Based on the amplitude of the control voltage and vco characteristic's, o/p spectrum will have huge sidebands around the carrier frequency corresponding to control voltage avg voltage. IN the worst case control voltage oscillates between 0 to Vdd, hence carrier frequency corresponding to vdd/2 with spurs at an offset of loop natural frequency.

Thanks,
Raj.

Title: Re: Analog PLL questions
Post by YYou on Dec 18^th, 2015, 11:48am

Hi Raj,

Thanks for the reply. You are right about question 1. My understanding is for mixer-type phase detector, the output (phase error) is a sinusoid, say sin(x). So the PD gain is at max. with zero phase error, and at min. with max. phase error. The loop gain will be very different for the areas in these two extreme cases. What is the methodology to pick the filter parameters for a stable loop ?

Thanks.

Title: Re: Analog PLL questions
Post by loose-electron on Dec 28^th, 2015, 4:13pm

If the loop is unstable it will not settle on frequency.
(will be seen as frequency oscillation around the reference frequency)

If the loop is marginally stable the control voltage will ring/overshoot if the frequency reference is shifted.

Go look through a textbook on PLL design there is a lot out there on control loops, zeta, damping and all that.